From: jason-jh.lin <jason-jh.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
"Philipp Zabel" <p.zabel@pengutronix.de>
Cc: Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
<hsinyi@chromium.org>, <fshao@chromium.org>,
<moudy.ho@mediatek.com>, <roy-cw.yeh@mediatek.com>,
<jason-jh.lin@mediatek.com>, Fabien Parent <fparent@baylibre.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
<nancy.lin@mediatek.com>, <singo.chang@mediatek.com>,
<devicetree@vger.kernel.org>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>
Subject: [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195
Date: Tue, 21 Sep 2021 23:52:07 +0800 [thread overview]
Message-ID: <20210921155218.10387-6-jason-jh.lin@mediatek.com> (raw)
In-Reply-To: <20210921155218.10387-1-jason-jh.lin@mediatek.com>
add MERGE additional properties description for mt8195:
1. async clock
2. fifo setting enable
3. reset controller
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,merge.yaml | 31 +++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
index 75beeb207ceb..542dd7137d3b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml
@@ -38,6 +38,19 @@ properties:
clocks:
items:
- description: MERGE Clock
+ - description: MERGE Async Clock
+ Controlling the synchronous process between MERGE and other display
+ function blocks cross clock domain.
+
+ mediatek,merge-fifo-en:
+ description:
+ The setting of merge fifo is mainly provided for the display latency
+ buffer to ensure that the back-end panel display data will not be
+ underrun, a little more data is needed in the fifo.
+ According to the merge fifo settings, when the water level is detected
+ to be insufficient, it will trigger RDMA sending ultra and preulra
+ command to SMI to speed up the data rate.
+ type: boolean
mediatek,gce-client-reg:
description:
@@ -50,6 +63,11 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
+ resets:
+ description: reset controller
+ See Documentation/devicetree/bindings/reset/reset.txt for details.
+ maxItems: 1
+
required:
- compatible
- reg
@@ -67,3 +85,16 @@ examples:
power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
clocks = <&mmsys CLK_MM_DISP_MERGE>;
};
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge","merge_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ mediatek,merge-fifo-en = <1>;
+ resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>;
+ };
--
2.18.0
next prev parent reply other threads:[~2021-09-21 15:52 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-21 15:52 [PATCH v11 00/16] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 01/16] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 02/16] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 03/16] dt-bindings: display: mediatek: disp: split each block to individual yaml jason-jh.lin
2021-09-24 23:41 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 04/16] dt-bindings: display: mediatek: dsc: add yaml for mt8195 SoC binding jason-jh.lin
2021-09-25 2:11 ` Chun-Kuang Hu
2021-09-21 15:52 ` jason-jh.lin [this message]
2021-09-25 2:17 ` [PATCH v11 05/16] dt-bindings: display: mediatek: merge: add additional prop for mt8195 Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 06/16] dt-bindings: display: mediatek: add mt8195 SoC binding for vdosys0 jason-jh.lin
2021-09-25 2:20 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 07/16] dt-bindings: arm: mediatek: move common module from display folder jason-jh.lin
2021-09-25 2:22 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 08/16] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 09/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2021-10-14 14:05 ` AngeloGioacchino Del Regno
2021-10-22 10:13 ` Jason-JH Lin
2021-10-25 5:05 ` Fei Shao
2021-10-25 5:33 ` Jason-JH Lin
2021-09-21 15:52 ` [PATCH v11 10/16] soc: mediatek: add mtk-mutex " jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 11/16] drm/mediatek: remove unused define in mtk_drm_ddp_comp.c jason-jh.lin
2021-09-21 15:52 ` [PATCH v11 12/16] drm/mediatek: rename the define of register offset jason-jh.lin
2021-09-29 14:59 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 13/16] drm/mediatek: adjust to the alphabetic order for mediatek-drm jason-jh.lin
2021-09-29 14:59 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 14/16] drm/mediatek: add DSC support " jason-jh.lin
2021-09-29 15:00 ` Chun-Kuang Hu
2021-09-21 15:52 ` [PATCH v11 15/16] drm/mediatek: add MERGE " jason-jh.lin
2021-10-14 14:27 ` AngeloGioacchino Del Regno
2021-10-22 10:30 ` Jason-JH Lin
2021-09-21 15:52 ` [PATCH v11 16/16] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
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