From: Michael Cheng <michael.cheng@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: tvrtko.ursulin@linux.intel.com, michael.cheng@intel.com,
wayne.boyer@intel.com, casey.g.bowman@intel.com,
lucas.demarchi@intel.com, dri-devel@lists.freedesktop.org
Subject: [PATCH v5 3/5] drm/i915/gt: Re-work reset_csb
Date: Fri, 4 Feb 2022 08:37:09 -0800 [thread overview]
Message-ID: <20220204163711.439403-4-michael.cheng@intel.com> (raw)
In-Reply-To: <20220204163711.439403-1-michael.cheng@intel.com>
Use drm_clflush_virt_range instead of directly invoking clflush. This
will prevent compiler errors when building for non-x86 architectures.
v2(Michael Cheng): Remove extra clflush
v3(Michael Cheng): Remove memory barrier since drm_clflush_virt_range
takes care of it.
Signed-off-by: Michael Cheng <michael.cheng@intel.com>
---
drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 7500c06562da..22505aa428d9 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2944,9 +2944,8 @@ reset_csb(struct intel_engine_cs *engine, struct i915_request **inactive)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
- mb(); /* paranoia: read the CSB pointers from after the reset */
- clflush(execlists->csb_write);
- mb();
+ drm_clflush_virt_range(execlists->csb_write,
+ sizeof(execlists->csb_write));
inactive = process_csb(engine, inactive); /* drain preemption events */
--
2.25.1
next prev parent reply other threads:[~2022-02-04 16:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-04 16:37 [PATCH v5 0/5] Use drm_clflush* instead of clflush Michael Cheng
2022-02-04 16:37 ` [PATCH v5 1/5] drm/i915/gt: Re-work intel_write_status_page Michael Cheng
2022-02-04 16:37 ` [PATCH v5 2/5] drm/i915/gt: Drop invalidate_csb_entries Michael Cheng
2022-02-07 11:57 ` Tvrtko Ursulin
2022-02-07 18:47 ` Michael Cheng
2022-02-04 16:37 ` Michael Cheng [this message]
2022-02-04 16:37 ` [PATCH v5 4/5] drm/i915/: Re-work clflush_write32 Michael Cheng
2022-02-04 16:37 ` [PATCH v5 5/5] drm/i915/gt: replace cache_clflush_range Michael Cheng
2022-02-07 12:03 ` [PATCH v5 0/5] Use drm_clflush* instead of clflush Tvrtko Ursulin
2022-02-07 12:44 ` [Intel-gfx] " Jani Nikula
2022-02-08 9:02 ` Tvrtko Ursulin
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