From: Lucas De Marchi <lucas.demarchi@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC
Date: Mon, 2 May 2022 11:39:48 -0700 [thread overview]
Message-ID: <20220502183948.2kjtwbqrixjbuc5j@ldmartin-desk2.jf.intel.com> (raw)
In-Reply-To: <YnALz9E2cNkAVnK0@mdroper-desk1.amr.corp.intel.com>
On Mon, May 02, 2022 at 09:50:23AM -0700, Matt Roper wrote:
>On Mon, May 02, 2022 at 09:34:09AM -0700, Matt Roper wrote:
>> From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>>
>> Bspec: 45101, 72161
>> Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>> Signed-off-by: Fei Yang <fei.yang@intel.com>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt_types.h | 1 +
>> drivers/gpu/drm/i915/gt/intel_mocs.c | 24 ++++++++++++++++++++-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 13 ++++++++---
>> drivers/gpu/drm/i915/i915_drv.h | 2 ++
>> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
>> drivers/gpu/drm/i915/intel_device_info.h | 1 +
>> 6 files changed, 39 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> index b06611c1d4ad..7853ea194ea6 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
>> @@ -221,6 +221,7 @@ struct intel_gt {
>>
>> struct {
>> u8 uc_index;
>> + u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
>> } mocs;
>>
>> struct intel_pxp pxp;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> index c4c37585ae8c..265812589f87 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
>> @@ -23,6 +23,7 @@ struct drm_i915_mocs_table {
>> unsigned int n_entries;
>> const struct drm_i915_mocs_entry *table;
>> u8 uc_index;
>> + u8 wb_index; /* Only for platforms listed in Bspec: 72161 */
>> u8 unused_entries_index;
>> };
>>
>> @@ -47,6 +48,7 @@ struct drm_i915_mocs_table {
>>
>> /* Helper defines */
>> #define GEN9_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
>> +#define PVC_NUM_MOCS_ENTRIES 3
>
>Should this be 4? The value here should reflect the number of entries
>that can defined in hardware rather than the size of the table we're
>asked to program. Since there are two registers (each with a high and a
>low entry), that would imply we should set 4 here to ensure that the
>fourth entry is initialized according to unused_entries_index rather
>than left at whatever the hardware defaults might be.
not sure I understand what you mean here. The n_entries specifies, as
you said, the number of entries we can have. Bspec 45101 shows entries
for indexes 0, 1 and 2. As does the pvc_mocs_table below.
Also, from bspec 44509:
"For PVC, only 3 MOCS states are supported. The allowed index values are
in range [0, 2]..."
So, I don't think we want to program any fourth entry.
Lucas De Marchi
next prev parent reply other threads:[~2022-05-02 18:39 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-02 16:34 [PATCH 00/11] i915: Introduce Ponte Vecchio Matt Roper
2022-05-02 16:34 ` [PATCH 01/11] drm/i915/pvc: add initial Ponte Vecchio definitions Matt Roper
2022-05-02 20:44 ` Lucas De Marchi
2022-05-02 16:34 ` [PATCH 02/11] drm/i915/pvc: Add forcewake support Matt Roper
2022-05-02 22:33 ` Summers, Stuart
2022-05-05 0:34 ` Matt Roper
2022-05-02 16:34 ` [PATCH 03/11] drm/i915/pvc: Define MOCS table for PVC Matt Roper
2022-05-02 16:50 ` Matt Roper
2022-05-02 18:39 ` Lucas De Marchi [this message]
2022-05-02 18:50 ` [Intel-gfx] " Matt Roper
2022-05-02 19:27 ` Lucas De Marchi
2022-05-02 19:42 ` Matt Roper
2022-05-02 21:03 ` Lucas De Marchi
2022-05-02 21:14 ` Matt Roper
2022-05-03 6:22 ` Lucas De Marchi
2022-05-02 16:34 ` [PATCH 04/11] drm/i915/pvc: Read correct RP_STATE_CAP register Matt Roper
2022-05-02 16:55 ` Rodrigo Vivi
2022-05-02 16:34 ` [PATCH 05/11] drm/i915/pvc: Remove additional 3D flags from PIPE_CONTROL Matt Roper
2022-05-02 16:34 ` [PATCH 06/11] drm/i915/pvc: Reduce stack usage in reset selftest with extra blitter engine Matt Roper
2022-05-02 18:46 ` Souza, Jose
2022-05-03 8:25 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-02 16:34 ` [PATCH 07/11] drm/i915/pvc: Engines definitions for new copy engines Matt Roper
2022-05-02 18:45 ` [Intel-gfx] " Souza, Jose
2022-05-03 8:05 ` Tvrtko Ursulin
2022-05-05 20:59 ` Matt Roper
2022-05-06 7:21 ` Tvrtko Ursulin
2022-05-06 14:29 ` Matt Roper
2022-05-02 16:34 ` [PATCH 08/11] drm/i915/pvc: Interrupt support " Matt Roper
2022-05-02 22:23 ` Summers, Stuart
2022-05-02 16:34 ` [PATCH 09/11] drm/i915/pvc: Reset " Matt Roper
2022-05-02 18:44 ` [Intel-gfx] " Souza, Jose
2022-05-02 22:23 ` Summers, Stuart
2022-05-02 16:34 ` [PATCH 10/11] drm/i915/pvc: skip all copy engines from aux table invalidate Matt Roper
2022-05-02 18:40 ` [Intel-gfx] " Souza, Jose
2022-05-02 22:58 ` Kumar Valsan, Prathap
2022-05-02 16:34 ` [PATCH 11/11] drm/i915/pvc: read fuses for link copy engines Matt Roper
2022-05-02 18:48 ` Souza, Jose
2022-05-03 8:19 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-03 8:21 ` [Intel-gfx] [PATCH 00/11] i915: Introduce Ponte Vecchio Tvrtko Ursulin
2022-05-03 14:56 ` Matt Roper
2022-05-03 15:01 ` Tvrtko Ursulin
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