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From: cyndis@kapsi.fi
To: thierry.reding@gmail.com, jonathanh@nvidia.com,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	digetx@gmail.com
Cc: linux-tegra@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
	Mikko Perttunen <mperttunen@nvidia.com>
Subject: [PATCH v1 02/13] dt-bindings: Add headers for Host1x and VIC on Tegra234
Date: Mon, 16 May 2022 13:02:02 +0300	[thread overview]
Message-ID: <20220516100213.1536571-3-cyndis@kapsi.fi> (raw)
In-Reply-To: <20220516100213.1536571-1-cyndis@kapsi.fi>

From: Mikko Perttunen <mperttunen@nvidia.com>

Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
 include/dt-bindings/clock/tegra234-clock.h     | 4 ++++
 include/dt-bindings/memory/tegra234-mc.h       | 5 +++++
 include/dt-bindings/power/tegra234-powergate.h | 1 +
 include/dt-bindings/reset/tegra234-reset.h     | 1 +
 4 files changed, 11 insertions(+)

diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index bd4c3086a2da..6e4e5cc75631 100644
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -38,6 +38,8 @@
  * throughput and memory controller power.
  */
 #define TEGRA234_CLK_EMC			31U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
+#define TEGRA234_CLK_HOST1X                     46U
 /** @brief output of gate CLK_ENB_FUSE */
 #define TEGRA234_CLK_FUSE			40U
 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
@@ -132,6 +134,8 @@
 #define TEGRA234_CLK_UARTA			155U
 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
 #define TEGRA234_CLK_PEX1_C6_CORE		161U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
+#define TEGRA234_CLK_VIC                        167U
 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
 #define TEGRA234_CLK_PEX2_C7_CORE		171U
 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index e3b0e9da295d..73fdd18523a9 100644
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -26,6 +26,8 @@
 #define TEGRA234_SID_PCIE8	0x09
 #define TEGRA234_SID_PCIE10	0x0b
 #define TEGRA234_SID_BPMP	0x10
+#define TEGRA234_SID_HOST1X	0x27
+#define TEGRA234_SID_VIC	0x34
 
 /*
  * memory client IDs
@@ -33,6 +35,7 @@
 
 /* High-definition audio (HDA) read clients */
 #define TEGRA234_MEMORY_CLIENT_HDAR 0x15
+#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
 /* PCIE6 read clients */
 #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
 /* PCIE6 write clients */
@@ -65,6 +68,8 @@
 #define TEGRA234_MEMORY_CLIENT_SDMMCRAB 0x63
 /* sdmmcd memory write client */
 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
+#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
+#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
 /* BPMP read client */
 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
 /* BPMP write client */
diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
index f610eee9bce8..c3f7e380d2c6 100644
--- a/include/dt-bindings/power/tegra234-powergate.h
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -18,5 +18,6 @@
 #define TEGRA234_POWER_DOMAIN_MGBEA	17U
 #define TEGRA234_POWER_DOMAIN_MGBEB	18U
 #define TEGRA234_POWER_DOMAIN_MGBEC	19U
+#define TEGRA234_POWER_DOMAIN_VIC       29U
 
 #endif
diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index 547ca3b60caa..1971400bf360 100644
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -44,6 +44,7 @@
 #define TEGRA234_RESET_QSPI1			77U
 #define TEGRA234_RESET_SDMMC4			85U
 #define TEGRA234_RESET_UARTA			100U
+#define TEGRA234_RESET_VIC                      113U
 #define TEGRA234_RESET_PEX0_CORE_0		116U
 #define TEGRA234_RESET_PEX0_CORE_1		117U
 #define TEGRA234_RESET_PEX0_CORE_2		118U
-- 
2.36.1


  parent reply	other threads:[~2022-05-16 10:02 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-16 10:02 [PATCH v1 00/13] Host1x support on Tegra234 cyndis
2022-05-16 10:02 ` [PATCH v1 01/13] dt-bindings: Add bindings for Tegra234 Host1x and VIC cyndis
2022-05-16 16:33   ` Rob Herring
2022-05-17  8:18     ` Mikko Perttunen
2022-05-16 10:02 ` cyndis [this message]
2022-05-17  8:02   ` [PATCH v1 02/13] dt-bindings: Add headers for Host1x and VIC on Tegra234 Krzysztof Kozlowski
2022-05-17  8:41     ` Mikko Perttunen
2022-05-17  8:43       ` Krzysztof Kozlowski
2022-05-17  8:48         ` Mikko Perttunen
2022-05-16 10:02 ` [PATCH v1 03/13] arm64: tegra: Add " cyndis
2022-05-17  8:01   ` Krzysztof Kozlowski
2022-05-17  8:38     ` Mikko Perttunen
2022-05-17 13:33       ` Krzysztof Kozlowski
2022-05-16 10:02 ` [PATCH v1 04/13] gpu: host1x: Deduplicate hardware headers cyndis
2022-05-16 10:02 ` [PATCH v1 05/13] gpu: host1x: Simplify register mapping and add common aperture cyndis
2022-05-16 10:02 ` [PATCH v1 06/13] gpu: host1x: Program virtualization tables cyndis
2022-05-16 10:02 ` [PATCH v1 07/13] gpu: host1x: Allow reset to be missing cyndis
2022-05-16 10:02 ` [PATCH v1 08/13] gpu: host1x: Program interrupt destinations on Tegra234 cyndis
2022-05-16 10:02 ` [PATCH v1 09/13] gpu: host1x: Tegra234 device data and headers cyndis
2022-05-16 10:02 ` [PATCH v1 10/13] gpu: host1x: Rewrite job opcode sequence cyndis
2022-05-16 10:02 ` [PATCH v1 11/13] gpu: host1x: Add MLOCK release code on Tegra234 cyndis
2022-05-16 10:02 ` [PATCH v1 12/13] gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+ cyndis
2022-05-16 10:02 ` [PATCH v1 13/13] drm/tegra: vic: Add Tegra234 support cyndis
2022-06-03  9:38 ` [PATCH v1 00/13] Host1x support on Tegra234 Dmitry Osipenko
2022-06-08 18:59   ` Mikko Perttunen

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