From: Marco Felsch <m.felsch@pengutronix.de>
To: robert.foss@linaro.org, laurent.pinchart@ideasonboard.com,
jernej.skrabec@gmail.com, jonas@kwiboo.se, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, sam@ravnborg.org,
maxime@cerno.tech
Cc: devicetree@vger.kernel.org, kernel@pengutronix.de,
dri-devel@lists.freedesktop.org
Subject: [PATCH 1/6] drm/bridge: ti-sn65dsi83: make lvds lane register setup more readable
Date: Mon, 30 May 2022 17:05:44 +0200 [thread overview]
Message-ID: <20220530150548.1236307-2-m.felsch@pengutronix.de> (raw)
In-Reply-To: <20220530150548.1236307-1-m.felsch@pengutronix.de>
No functional change. Just reuse the already existing val variable to
setup the register. This is in preparation for adding the new feature to
reverse the CHA/CHB lane orders. Without this change this call gets very
unreadable.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
drivers/gpu/drm/bridge/ti-sn65dsi83.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
index 2831f0813c3a..112fea004c8e 100644
--- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
+++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
@@ -437,11 +437,12 @@ static void sn65dsi83_atomic_enable(struct drm_bridge *bridge,
regmap_write(ctx->regmap, REG_LVDS_FMT, val);
regmap_write(ctx->regmap, REG_LVDS_VCOM, 0x05);
- regmap_write(ctx->regmap, REG_LVDS_LANE,
- (ctx->lvds_dual_link_even_odd_swap ?
- REG_LVDS_LANE_EVEN_ODD_SWAP : 0) |
- REG_LVDS_LANE_CHA_LVDS_TERM |
- REG_LVDS_LANE_CHB_LVDS_TERM);
+
+ val = REG_LVDS_LANE_CHA_LVDS_TERM | REG_LVDS_LANE_CHB_LVDS_TERM;
+ if (ctx->lvds_dual_link_even_odd_swap)
+ val |= REG_LVDS_LANE_EVEN_ODD_SWAP;
+
+ regmap_write(ctx->regmap, REG_LVDS_LANE, val);
regmap_write(ctx->regmap, REG_LVDS_CM, 0x00);
le16val = cpu_to_le16(mode->hdisplay);
--
2.30.2
next prev parent reply other threads:[~2022-05-30 15:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-30 15:05 [PATCH 0/6] TI SN65DSI83 Features Marco Felsch
2022-05-30 15:05 ` Marco Felsch [this message]
2022-05-30 15:05 ` [PATCH 2/6] dt-bindings: drm/bridge: ti-sn65dsi83: add documentation for reverse lvds lanes Marco Felsch
2022-06-05 21:09 ` Rob Herring
2022-05-30 15:05 ` [PATCH 3/6] drm/bridge: ti-sn65dsi83: add support to swap the LVDS data lanes Marco Felsch
2022-05-30 15:05 ` [PATCH 4/6] drm/bridge: ti-sn65dsi83: make use of dev_err_probe Marco Felsch
2022-05-30 15:05 ` [PATCH 5/6] dt-bindings: drm/bridge: ti-sn65dsi83: Add reset controller documentation Marco Felsch
2022-05-31 7:33 ` (EXT) " Alexander Stein
2022-05-31 8:29 ` Marco Felsch
2022-05-30 15:05 ` [PATCH 6/6] drm/bridge: ti-sn65dsi83: add support for a external reset controller Marco Felsch
2022-07-26 9:12 ` [PATCH 0/6] TI SN65DSI83 Features Marco Felsch
2022-08-29 15:06 ` Robert Foss
2022-08-31 8:13 ` Marco Felsch
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