From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0FEC9C43334 for ; Mon, 13 Jun 2022 14:48:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1AC2810E82F; Mon, 13 Jun 2022 14:48:49 +0000 (UTC) Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0BBC710E81F for ; Mon, 13 Jun 2022 14:48:46 +0000 (UTC) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id B8E70320092F; Mon, 13 Jun 2022 10:48:44 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 13 Jun 2022 10:48:45 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cerno.tech; h=cc :cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1655131724; x=1655218124; bh=gs Z+0dF52jGkjphNjY9ehU/ZgQc7Gx9ag0fLRQvtymQ=; b=cpEyHUL5LVh/qFykau KH7BRNaRphYKbp71IM6pi9WAjTfYE4oNEH9n5/SwHXKOhgTJ/rEzP83A7Lx9YHcA 6LBQhVr18FXcU+GAwqEpxHNp/s2gmJhQO5MN7SKzTyIwe+zKv0i8OubiwRHFiU6Z UGrLf5OhwgS/iKvuKyQ+5niXaOR2LMIfJ/r9BXDDX0dDK7WB/xrANT1NJXvJgHHt nYLfQwfbNJdVBQUI9GQWatBUtuqandIw9avD2PN2R5a5UB61sWfO15G6o7JLna4J S8R/CVtb4y7ETn/yWaRba2SC3mrZnL10pUZFXq65jGg0U+bIDEDZdRfjj34iJH8q +12Q== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm2; t=1655131724; x=1655218124; bh=gsZ+0dF52jGkj phNjY9ehU/ZgQc7Gx9ag0fLRQvtymQ=; b=h/kJl0dcGFPzBwN/qnU4wT0gF9ket pSRnq4N3FiDK7cyVkhSVUzMGo/eGVGM8ZWnWEQ437UyyMhUXKK9VoCGdIvRp1vWO O8Ey9NQDHeCdq1U36oRPJwOaMv2w5jzHXJLsl84acDx5t4IQbZmNbi7V2XpFq6ld ff78Y4ISWdU/YAClG1kpW/Zn45tsyVpmfFwKtoE4mZ5pdQhj3UeCRzHuyFDIWkxN uZWSoywfP5h3pO6aJBC14mzqlukr37M6uZw4wslZFaI4GUU7U5fKDmQUxUDR6cuS LSpl6+PYPlMEvSaQ6u3V31XIZNuaVX3SzNv2l4OSgQgCbj4tlNx/bp/1A== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedruddujedgjeelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrgihi mhgvucftihhprghrugcuoehmrgigihhmvgestggvrhhnohdrthgvtghhqeenucggtffrrg htthgvrhhnpeelkeefteduhfekjeeihfetudfguedvveekkeetteekhfekhfdtlefgfedu vdejhfenucevlhhushhtvghrufhiiigvpeeinecurfgrrhgrmhepmhgrihhlfhhrohhmpe hmrgigihhmvgestggvrhhnohdrthgvtghh X-ME-Proxy: Feedback-ID: i8771445c:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 13 Jun 2022 10:48:43 -0400 (EDT) From: Maxime Ripard To: Daniel Vetter , David Airlie , Maarten Lankhorst , Thomas Zimmermann , Maxime Ripard Subject: [PATCH 13/33] drm/vc4: dsi: Correct pixel order for DSI0 Date: Mon, 13 Jun 2022 16:47:40 +0200 Message-Id: <20220613144800.326124-14-maxime@cerno.tech> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220613144800.326124-1-maxime@cerno.tech> References: <20220613144800.326124-1-maxime@cerno.tech> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org, Dave Stevenson Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Dave Stevenson For slightly unknown reasons, dsi0 takes a different pixel format to dsi1, and that has to be set in the pixel valve. Amend the setup accordingly. Fixes: a86773d120d7 ("drm/vc4: Add support for feeding DSI encoders from the pixel valve.") Signed-off-by: Dave Stevenson Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_crtc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 59b20c8f132b..f74270ad3e13 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -319,7 +319,8 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encode u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); - u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; + bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; + u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; u8 ppc = pv_data->pixels_per_clock; bool debug_dump_regs = false; -- 2.36.1