From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD
Date: Thu, 1 Sep 2022 23:03:34 -0700 [thread overview]
Message-ID: <20220902060342.151824-4-radhakrishna.sripada@intel.com> (raw)
In-Reply-To: <20220902060342.151824-1-radhakrishna.sripada@intel.com>
From: José Roberto de Souza <jose.souza@intel.com>
The GMD step field do not properly match the current stepping convention
that we use(STEP_A0, STEP_A1, STEP_B0...).
One platform could have { arch = 12, rel = 70, step = 1 } and the
actual stepping is STEP_B0 but without the translation of the step
field would mean STEP_A1.
That is why we will need to have gmd_to_intel_step tables for each IP.
v2:
- Pass the updated ip version structure
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_step.c | 60 +++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_step.c b/drivers/gpu/drm/i915/intel_step.c
index 42b3133d8387..14ea103d6dab 100644
--- a/drivers/gpu/drm/i915/intel_step.c
+++ b/drivers/gpu/drm/i915/intel_step.c
@@ -135,6 +135,48 @@ static const struct intel_step_info adlp_n_revids[] = {
[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
};
+struct gmd_to_intel_step {
+ struct ip_version gmd;
+ enum intel_step step;
+};
+
+static const struct gmd_to_intel_step gmd_graphics_table[] = {
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 71, .gmd.step = 4, .step = STEP_B0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 12, .gmd.rel = 73, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_media_table[] = {
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 13, .gmd.rel = 70, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static const struct gmd_to_intel_step gmd_display_table[] = {
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 0, .step = STEP_A0 },
+ { .gmd.ver = 14, .gmd.rel = 0, .gmd.step = 4, .step = STEP_B0 },
+};
+
+static u8 gmd_to_intel_step(struct drm_i915_private *i915,
+ struct ip_version *gmd,
+ const struct gmd_to_intel_step *table,
+ int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ if (table[i].gmd.ver == gmd->ver &&
+ table[i].gmd.rel == gmd->rel &&
+ table[i].gmd.step == gmd->step)
+ return table[i].step;
+ }
+
+ drm_dbg(&i915->drm, "Using future steppings\n");
+ return STEP_FUTURE;
+}
+
static void pvc_step_init(struct drm_i915_private *i915, int pci_revid);
void intel_step_init(struct drm_i915_private *i915)
@@ -144,6 +186,24 @@ void intel_step_init(struct drm_i915_private *i915)
int revid = INTEL_REVID(i915);
struct intel_step_info step = {};
+ if (HAS_GMD_ID(i915)) {
+ step.graphics_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->graphics.version,
+ gmd_graphics_table,
+ ARRAY_SIZE(gmd_graphics_table));
+ step.media_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->media.version,
+ gmd_media_table,
+ ARRAY_SIZE(gmd_media_table));
+ step.display_step = gmd_to_intel_step(i915,
+ &RUNTIME_INFO(i915)->display.version,
+ gmd_display_table,
+ ARRAY_SIZE(gmd_display_table));
+ RUNTIME_INFO(i915)->step = step;
+
+ return;
+ }
+
if (IS_PONTEVECCHIO(i915)) {
pvc_step_init(i915, revid);
return;
--
2.34.1
next prev parent reply other threads:[~2022-09-02 6:05 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-02 6:03 [PATCH v4 00/11] Initial Meteorlake Support Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 01/11] drm/i915: Move display and media IP version to runtime info Radhakrishna Sripada
2022-09-02 16:49 ` kernel test robot
2022-09-02 22:10 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 17:21 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 02/11] drm/i915: Read graphics/media/display arch version from hw Radhakrishna Sripada
2022-09-07 20:49 ` [Intel-gfx] " Lucas De Marchi
2022-09-07 22:13 ` Matt Roper
2022-09-07 22:21 ` Lucas De Marchi
2022-09-07 22:38 ` Sripada, Radhakrishna
2022-09-07 23:32 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-02 6:03 ` Radhakrishna Sripada [this message]
2022-09-08 17:42 ` [Intel-gfx] [PATCH v4 03/11] drm/i915: Parse and set stepping for platforms with GMD Matt Roper
2022-09-02 6:03 ` [PATCH v4 04/11] drm/i915/mtl: Define engine context layouts Radhakrishna Sripada
2022-09-06 12:16 ` Balasubramani Vivekanandan
2022-09-07 23:33 ` [PATCH v4.1] " Radhakrishna Sripada
2022-09-08 18:00 ` [Intel-gfx] " Matt Roper
2022-09-02 6:03 ` [PATCH v4 05/11] drm/i915/mtl: Add gmbus and gpio support Radhakrishna Sripada
2022-09-08 13:05 ` [Intel-gfx] " Balasubramani Vivekanandan
2022-09-08 18:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 06/11] drm/i915/mtl: Add display power wells Radhakrishna Sripada
2022-09-08 18:07 ` Matt Roper
2022-09-08 18:11 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 07/11] drm/i915/mtl: Add DP AUX support on TypeC ports Radhakrishna Sripada
2022-09-08 18:13 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 08/11] drm/i915/mtl: Obtain SAGV values from MMIO instead of GT pcode mailbox Radhakrishna Sripada
2022-09-02 6:03 ` [PATCH v4 09/11] drm/i915/mtl: Update MBUS_DBOX credits Radhakrishna Sripada
2022-09-08 20:02 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 10/11] drm/i915/mtl: Update CHICKEN_TRANS* register addresses Radhakrishna Sripada
2022-09-08 20:30 ` Matt Roper
2022-09-02 6:03 ` [PATCH v4 11/11] drm/i915/mtl: Do not update GV point, mask value Radhakrishna Sripada
2022-09-09 17:14 ` [Intel-gfx] " Balasubramani Vivekanandan
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