From: Marijn Suijten <marijn.suijten@somainline.org>
To: phone-devel@vger.kernel.org, Rob Clark <robdclark@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Vinod Koul <vkoul@kernel.org>
Cc: freedreno@lists.freedesktop.org,
Douglas Anderson <dianders@chromium.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Jami Kettunen <jami.kettunen@somainline.org>,
Vladimir Lypak <vladimir.lypak@gmail.com>,
linux-arm-msm@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
dri-devel@lists.freedesktop.org,
Javier Martinez Canillas <javierm@redhat.com>,
David Airlie <airlied@linux.ie>,
Martin Botka <martin.botka@somainline.org>,
~postmarketos/upstreaming@lists.sr.ht,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@somainline.org>,
Alex Deucher <alexander.deucher@amd.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
Sean Paul <sean@poorly.run>,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 7/7] drm/msm/dsi: Prevent signed BPG offsets from bleeding into adjacent bits
Date: Wed, 5 Oct 2022 20:16:57 +0200 [thread overview]
Message-ID: <20221005181657.784375-8-marijn.suijten@somainline.org> (raw)
In-Reply-To: <20221005181657.784375-1-marijn.suijten@somainline.org>
The bpg_offset array contains negative BPG offsets which fill the full 8
bits of a char thanks to two's complement: this however results in those
bits bleeding into the next field when the value is packed into DSC PPS
by the drm_dsc_helper function, which only expects range_bpg_offset to
contain 6-bit wide values. As a consequence random slices appear
corrupted on-screen (tested on a Sony Tama Akatsuki device with sdm845).
Use AND operators to limit these two's complement values to 6 bits,
similar to the AMD and i915 drivers.
Fixes: b9080324d6ca ("drm/msm/dsi: add support for dsc data")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 4717d49d76be..b3cff3d3aa85 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -1806,7 +1806,11 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc
for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
dsc->rc_range_params[i].range_min_qp = min_qp[i];
dsc->rc_range_params[i].range_max_qp = max_qp[i];
- dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i];
+ /*
+ * Range BPG Offset contains two's-complement signed values that fill
+ * 8 bits, yet the registers and DCS PPS field are only 6 bits wide.
+ */
+ dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK;
}
dsc->initial_offset = 6144; /* Not bpp 12 */
--
2.38.0
prev parent reply other threads:[~2022-10-05 18:17 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-05 18:16 [PATCH v2 0/7] drm/msm: Fix math issues in MSM DSC implementation Marijn Suijten
2022-10-05 18:16 ` [PATCH v2 1/7] drm/msm/dsi: Remove useless math in DSC calculations Marijn Suijten
2022-10-05 21:14 ` Abhinav Kumar
2022-10-05 18:16 ` [PATCH v2 2/7] drm/msm/dsi: Remove repeated calculation of slice_per_intf Marijn Suijten
2022-10-05 18:16 ` [PATCH v2 3/7] drm/msm/dsi: Use DIV_ROUND_UP instead of conditional increment on modulo Marijn Suijten
2022-10-05 21:34 ` Abhinav Kumar
2022-10-05 18:16 ` [PATCH v2 4/7] drm/msm/dsi: Reuse earlier computed dsc->slice_chunk_size Marijn Suijten
2022-10-05 21:37 ` Abhinav Kumar
2022-10-05 18:16 ` [PATCH v2 5/7] drm/msm/dsi: Account for DSC's bits_per_pixel having 4 fractional bits Marijn Suijten
2022-10-05 19:31 ` Dmitry Baryshkov
2022-10-05 20:58 ` Marijn Suijten
2022-10-05 21:06 ` Dmitry Baryshkov
2022-10-05 21:08 ` Marijn Suijten
2022-10-05 21:11 ` Dmitry Baryshkov
2022-10-05 21:33 ` Marijn Suijten
2022-10-05 18:16 ` [PATCH v2 6/7] drm/msm/dpu1: " Marijn Suijten
2022-10-05 18:16 ` Marijn Suijten [this message]
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