From: John.C.Harrison@Intel.com
To: Intel-GFX@Lists.FreeDesktop.Org
Cc: "Daniel Vetter" <daniel.vetter@ffwll.ch>,
DRI-Devel@Lists.FreeDesktop.Org,
"Chris Wilson" <chris@chris-wilson.co.uk>,
"Stuart Summers" <stuart.summers@intel.com>,
"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
"Jason Ekstrand" <jason@jlekstrand.net>,
"Akeem G Abodunrin" <akeem.g.abodunrin@intel.com>,
"Matthew Brost" <matthew.brost@intel.com>,
"Matthew Auld" <matthew.auld@intel.com>,
"Ramalingam C" <ramalingam.c@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Jani Nikula" <jani.nikula@intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Aravind Iddamsetty" <aravind.iddamsetty@intel.com>,
"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
"Michał Winiarski" <michal.winiarski@intel.com>,
"Tvrtko Ursulin" <tvrtko.ursulin@intel.com>,
"Tejas Upadhyay" <tejaskumarx.surendrakumar.upadhyay@intel.com>,
"Umesh Nerlige Ramappa" <umesh.nerlige.ramappa@intel.com>,
"John Harrison" <John.C.Harrison@Intel.com>
Subject: [PATCH v5 2/4] drm/i915: Fix compute pre-emption w/a to apply to compute engines
Date: Thu, 6 Oct 2022 14:38:11 -0700 [thread overview]
Message-ID: <20221006213813.1563435-3-John.C.Harrison@Intel.com> (raw)
In-Reply-To: <20221006213813.1563435-1-John.C.Harrison@Intel.com>
From: John Harrison <John.C.Harrison@Intel.com>
An earlier patch added support for compute engines. However, it missed
enabling the anti-pre-emption w/a for the new engine class. So move
the 'compute capable' flag earlier and use it for the pre-emption w/a
test.
Fixes: c674c5b9342e ("drm/i915/xehp: CCS should use RCS setup functions")
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: "Michał Winiarski" <michal.winiarski@intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 24 +++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8f16955f0821e..fcbccd8d244e9 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -486,6 +486,17 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
engine->logical_mask = BIT(logical_instance);
__sprint_engine_name(engine);
+ if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
+ __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
+ engine->class == RENDER_CLASS)
+ engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
+
+ /* features common between engines sharing EUs */
+ if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
+ engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+ engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
+ }
+
engine->props.heartbeat_interval_ms =
CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
engine->props.max_busywait_duration_ns =
@@ -498,20 +509,9 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
CONFIG_DRM_I915_TIMESLICE_DURATION;
/* Override to uninterruptible for OpenCL workloads. */
- if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
+ if (GRAPHICS_VER(i915) == 12 && (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
engine->props.preempt_timeout_ms = 0;
- if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
- __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
- engine->class == RENDER_CLASS)
- engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
-
- /* features common between engines sharing EUs */
- if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
- engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
- engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
- }
-
/* Cap properties according to any system limits */
#define CLAMP_PROP(field) \
do { \
--
2.37.3
next prev parent reply other threads:[~2022-10-06 21:37 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-06 21:38 [PATCH v5 0/4] Improve anti-pre-emption w/a for compute workloads John.C.Harrison
2022-10-06 21:38 ` [PATCH v5 1/4] drm/i915/guc: Limit scheduling properties to avoid overflow John.C.Harrison
2022-10-18 0:06 ` Ceraolo Spurio, Daniele
2022-10-06 21:38 ` John.C.Harrison [this message]
2022-10-06 21:38 ` [PATCH v5 3/4] drm/i915: Make the heartbeat play nice with long pre-emption timeouts John.C.Harrison
2022-10-07 8:44 ` [Intel-gfx] " Tvrtko Ursulin
2022-10-06 21:38 ` [PATCH v5 4/4] drm/i915: Improve long running compute w/a for GuC submission John.C.Harrison
2022-10-18 0:09 ` Ceraolo Spurio, Daniele
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