From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
Akhil P Oommen <quic_akhilpo@quicinc.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Rob Clark <robdclark@chromium.org>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
freedreno@lists.freedesktop.org
Subject: [PATCH v9 01/20] dt-bindings: display/msm: gpu: Document GMU wrapper-equipped A6xx
Date: Fri, 16 Jun 2023 01:20:42 +0200 [thread overview]
Message-ID: <20230223-topic-gmuwrapper-v9-1-890d8f470c8b@linaro.org> (raw)
In-Reply-To: <20230223-topic-gmuwrapper-v9-0-890d8f470c8b@linaro.org>
The "GMU Wrapper" is Qualcomm's name for "let's treat the GPU blocks
we'd normally assign to the GMU as if they were a part of the GMU, even
though they are not". It's a (good) software representation of the GMU_CX
and GMU_GX register spaces within the GPUSS that helps us programatically
treat these de-facto GMU-less parts in a way that's very similar to their
GMU-equipped cousins, massively saving up on code duplication.
The "wrapper" register space was specifically designed to mimic the layout
of a real GMU, though it rather obviously does not have the M3 core et al.
GMU wrapper-equipped A6xx GPUs require clocks and clock-names to be
specified under the GPU node, just like their older cousins. Account
for that.
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/display/msm/gpu.yaml | 61 ++++++++++++++++++----
1 file changed, 52 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index 5dabe7b6794b..58ca8912a8c3 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -36,10 +36,7 @@ properties:
reg-names:
minItems: 1
- items:
- - const: kgsl_3d0_reg_memory
- - const: cx_mem
- - const: cx_dbgc
+ maxItems: 3
interrupts:
maxItems: 1
@@ -157,16 +154,62 @@ allOf:
required:
- clocks
- clock-names
+
- if:
properties:
compatible:
contains:
- pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
-
- then: # Since Adreno 6xx series clocks should be defined in GMU
+ enum:
+ - qcom,adreno-610.0
+ - qcom,adreno-619.1
+ then:
properties:
- clocks: false
- clock-names: false
+ clocks:
+ minItems: 6
+ maxItems: 6
+
+ clock-names:
+ items:
+ - const: core
+ description: GPU Core clock
+ - const: iface
+ description: GPU Interface clock
+ - const: mem_iface
+ description: GPU Memory Interface clock
+ - const: alt_mem_iface
+ description: GPU Alternative Memory Interface clock
+ - const: gmu
+ description: CX GMU clock
+ - const: xo
+ description: GPUCC clocksource clock
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_dbgc
+
+ required:
+ - clocks
+ - clock-names
+ else:
+ if:
+ properties:
+ compatible:
+ contains:
+ pattern: '^qcom,adreno-6[0-9][0-9]\.[0-9]$'
+
+ then: # Starting with A6xx, the clocks are usually defined in the GMU node
+ properties:
+ clocks: false
+ clock-names: false
+
+ reg-names:
+ minItems: 1
+ items:
+ - const: kgsl_3d0_reg_memory
+ - const: cx_mem
+ - const: cx_dbgc
examples:
- |
--
2.41.0
next prev parent reply other threads:[~2023-06-15 23:21 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-15 23:20 [PATCH v9 00/20] GMU-less A6xx support (A610, A619_holi) Konrad Dybcio
2023-06-15 23:20 ` Konrad Dybcio [this message]
2023-06-15 23:20 ` [PATCH v9 02/20] dt-bindings: display/msm/gmu: Add GMU wrapper Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 03/20] drm/msm/adreno: Use adreno_is_revn for A690 Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 04/20] drm/msm/a6xx: Remove static keyword from sptprac en/disable functions Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 05/20] drm/msm/a6xx: Move force keepalive vote removal to a6xx_gmu_force_off() Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 06/20] drm/msm/a6xx: Move a6xx_bus_clear_pending_transactions to a6xx_gpu Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 07/20] drm/msm/a6xx: Improve a6xx_bus_clear_pending_transactions() Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 08/20] drm/msm/a6xx: Add a helper for software-resetting the GPU Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 09/20] drm/msm/a6xx: Remove both GBIF and RBBM GBIF halt on hw init Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 10/20] drm/msm/a6xx: Extend and explain UBWC config Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 11/20] drm/msm/a6xx: Move CX GMU power counter enablement to hw_init Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 12/20] drm/msm/a6xx: Introduce GMU wrapper support Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 13/20] drm/msm/adreno: Disable has_cached_coherent in GMU wrapper configurations Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 14/20] drm/msm/a6xx: Add support for A619_holi Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 15/20] drm/msm/a6xx: Add A610 support Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 16/20] drm/msm/a6xx: Fix some A619 tunables Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 17/20] drm/msm/a6xx: Use "else if" in GPU speedbin rev matching Konrad Dybcio
2023-06-15 23:20 ` [PATCH v9 18/20] drm/msm/a6xx: Use adreno_is_aXYZ macros in speedbin matching Konrad Dybcio
2023-06-15 23:21 ` [PATCH v9 19/20] drm/msm/a6xx: Add A619_holi speedbin support Konrad Dybcio
2023-06-15 23:21 ` [PATCH v9 20/20] drm/msm/a6xx: Add A610 " Konrad Dybcio
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