Hi all, On Tue, 30 May 2023 11:57:52 +1000 Stephen Rothwell wrote: > > @@@ -920,33 -587,8 +640,9 @@@ static const struct intel_device_info j > #define GEN12_FEATURES \ > GEN11_FEATURES, \ > GEN(12), \ > - .display.abox_mask = GENMASK(2, 1), \ > - .__runtime.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \ > - .__runtime.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \ > - BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \ > - BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ > - .display.pipe_offsets = { \ > - [TRANSCODER_A] = PIPE_A_OFFSET, \ > - [TRANSCODER_B] = PIPE_B_OFFSET, \ > - [TRANSCODER_C] = PIPE_C_OFFSET, \ > - [TRANSCODER_D] = PIPE_D_OFFSET, \ > - [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \ > - [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \ > - }, \ > - .display.trans_offsets = { \ > - [TRANSCODER_A] = TRANSCODER_A_OFFSET, \ > - [TRANSCODER_B] = TRANSCODER_B_OFFSET, \ > - [TRANSCODER_C] = TRANSCODER_C_OFFSET, \ > - [TRANSCODER_D] = TRANSCODER_D_OFFSET, \ > - [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \ > - [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \ > - }, \ > - TGL_CURSOR_OFFSETS, \ > - TGL_CACHELEVEL, \ > ++ .max_pat_index = 3 \ I fixed the above up to have a ',' after the '3' > .has_global_mocs = 1, \ > - .has_pxp = 1, \ > - .display.has_dsb = 1, \ > - .max_pat_index = 3 > + .has_pxp = 1 -- Cheers, Stephen Rothwell