From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A2542C54E58 for ; Wed, 20 Mar 2024 20:11:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0EE0D10E6B7; Wed, 20 Mar 2024 20:11:33 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Iwy1H/Z9"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by gabe.freedesktop.org (Postfix) with ESMTPS id F2ACB10E6B7; Wed, 20 Mar 2024 20:11:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1710965491; x=1742501491; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ly6p1Y33UBPvpoptNwEzwhg8CPrlAMNgKErWdAIka3w=; b=Iwy1H/Z98N6F2Axe5t1/eo6DT3hJQbCC9mknF3XfqTimfnK+NAsncl/u GXQgC9CIyEjwg+x7J4c9nVfn9jR/nJKlSUFMs/oAlBiGyxi73NKtOEk3Y C7qTLEBgtTJkNQO3Yp5RvuPPwnvumOk0tOG++azfYPeg7Lw3umLUBB08X FgNjYhdBchq03rc2QQPUbkYeE+sUyOjmsMDasp+FAX38ZP1zNojFJwmV+ MeQVq7JSwggXEqtuVW2Bo5BXsjy9IlBb9IbL0fxSc8qIZtn2ZJzO180JY AGIXSzjbXBm29VnM1eSCriGr8Qsmqg889b6hiNmOf7QhEedqHFCqewz7g g==; X-IronPort-AV: E=McAfee;i="6600,9927,11019"; a="31352339" X-IronPort-AV: E=Sophos;i="6.07,141,1708416000"; d="scan'208";a="31352339" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2024 13:11:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,141,1708416000"; d="scan'208";a="14246517" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Mar 2024 13:11:30 -0700 From: Imre Deak To: intel-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Subject: [PATCH 07/11] drm/dp: Add drm_dp_uhbr_channel_coding_supported() Date: Wed, 20 Mar 2024 22:11:47 +0200 Message-ID: <20240320201152.3487892-8-imre.deak@intel.com> X-Mailer: git-send-email 2.43.3 In-Reply-To: <20240320201152.3487892-1-imre.deak@intel.com> References: <20240320201152.3487892-1-imre.deak@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Factor out a function to check for UHBR channel coding support used by a follow-up patch in the patchset. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- include/drm/display/drm_dp_helper.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index dbe65651bf277..1d13a1ba2b97d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -217,7 +217,7 @@ static void intel_dp_set_dpcd_sink_rates(struct intel_dp *intel_dp) * Sink rates for 128b/132b. If set, sink should support all 8b/10b * rates and 10 Gbps. */ - if (intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B) { + if (drm_dp_uhbr_channel_coding_supported(intel_dp->dpcd)) { u8 uhbr_rates = 0; BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3); diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index a62fcd051d4d4..150c37a99a16f 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -221,6 +221,12 @@ drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B; } +static inline bool +drm_dp_uhbr_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B; +} + static inline bool drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) { -- 2.43.3