From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46F37C11F68 for ; Wed, 30 Jun 2021 10:08:26 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 172E761D0F for ; Wed, 30 Jun 2021 10:08:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 172E761D0F Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D4016E983; Wed, 30 Jun 2021 10:08:25 +0000 (UTC) Received: from so254-9.mailgun.net (so254-9.mailgun.net [198.61.254.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 018B26E982 for ; Wed, 30 Jun 2021 10:08:19 +0000 (UTC) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1625047703; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=V2ANtGMjJP031vwtea0cvuT0DcS61OO8FRdPjBQ676g=; b=nE3fi14tsM6QttDih2ox6Qkd7EMh8HRns8PjZujky8AoQGZkUJX1/06/UEbiQkj9KBbveTSb GrccMIZUQHArm3m5LMFMX+Xb6NXYPO8e3+Cvi8C1bTopeLnJOPRmTYFhwpMlBwS9h4eVnL5L YkHfioWOF7srGwO+fveBjVl7WNE= X-Mailgun-Sending-Ip: 198.61.254.9 X-Mailgun-Sid: WyJkOTU5ZSIsICJkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n06.prod.us-west-2.postgun.com with SMTP id 60dc4280ad0600eede606bf9 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Wed, 30 Jun 2021 10:08:00 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 5AB60C4338A; Wed, 30 Jun 2021 10:08:00 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 17A87C433D3; Wed, 30 Jun 2021 10:07:59 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Wed, 30 Jun 2021 15:37:59 +0530 From: Sai Prakash Ranjan To: Will Deacon Subject: Re: [PATCH 2/3] iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag In-Reply-To: <20210325173311.GA15504@willie-the-truck> References: <3f589e7de3f9fa93e84c83420c5270c546a0c368.1610372717.git.saiprakash.ranjan@codeaurora.org> <20210129090516.GB3998@willie-the-truck> <5d23fce629323bcda71594010824aad0@codeaurora.org> <20210201111556.GA7172@willie-the-truck> <20210201182016.GA21629@jcrouse1-lnx.qualcomm.com> <7e9aade14d0b7f69285852ade4a5a9f4@codeaurora.org> <20210203214612.GB19847@willie-the-truck> <4988e2ef35f76a0c2f1fe3f66f023a3b@codeaurora.org> <9362873a3bcf37cdd073a6128f29c683@codeaurora.org> <20210325173311.GA15504@willie-the-truck> Message-ID: <21239ba603d0bdc4e4c696588a905f88@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Isaac J. Manjarres" , David Airlie , Sean Paul , Linux Kernel Mailing List , dri-devel , Akhil P Oommen , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Kristian H Kristensen , linux-arm-msm , freedreno , linux-arm-kernel@lists.infradead.org, Robin Murphy Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Will, On 2021-03-25 23:03, Will Deacon wrote: > On Tue, Mar 09, 2021 at 12:10:44PM +0530, Sai Prakash Ranjan wrote: >> On 2021-02-05 17:38, Sai Prakash Ranjan wrote: >> > On 2021-02-04 03:16, Will Deacon wrote: >> > > On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote: >> > > > On 2021-02-01 23:50, Jordan Crouse wrote: >> > > > > On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote: >> > > > > > On Mon, Feb 1, 2021 at 3:16 AM Will Deacon wrote: >> > > > > > > On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote: >> > > > > > > > On 2021-01-29 14:35, Will Deacon wrote: >> > > > > > > > > On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ranjan wrote: >> > > > > > > > > > +#define IOMMU_LLC (1 << 6) >> > > > > > > > > >> > > > > > > > > On reflection, I'm a bit worried about exposing this because I think it >> > > > > > > > > will >> > > > > > > > > introduce a mismatched virtual alias with the CPU (we don't even have a >> > > > > > > > > MAIR >> > > > > > > > > set up for this memory type). Now, we also have that issue for the PTW, >> > > > > > > > > but >> > > > > > > > > since we always use cache maintenance (i.e. the streaming API) for >> > > > > > > > > publishing the page-tables to a non-coheren walker, it works out. >> > > > > > > > > However, >> > > > > > > > > if somebody expects IOMMU_LLC to be coherent with a DMA API coherent >> > > > > > > > > allocation, then they're potentially in for a nasty surprise due to the >> > > > > > > > > mismatched outer-cacheability attributes. >> > > > > > > > > >> > > > > > > > >> > > > > > > > Can't we add the syscached memory type similar to what is done on android? >> > > > > > > >> > > > > > > Maybe. How does the GPU driver map these things on the CPU side? >> > > > > > >> > > > > > Currently we use writecombine mappings for everything, although there >> > > > > > are some cases that we'd like to use cached (but have not merged >> > > > > > patches that would give userspace a way to flush/invalidate) >> > > > > > >> > > > > >> > > > > LLC/system cache doesn't have a relationship with the CPU cache. Its >> > > > > just a >> > > > > little accelerator that sits on the connection from the GPU to DDR and >> > > > > caches >> > > > > accesses. The hint that Sai is suggesting is used to mark the buffers as >> > > > > 'no-write-allocate' to prevent GPU write operations from being cached in >> > > > > the LLC >> > > > > which a) isn't interesting and b) takes up cache space for read >> > > > > operations. >> > > > > >> > > > > Its easiest to think of the LLC as a bonus accelerator that has no cost >> > > > > for >> > > > > us to use outside of the unfortunate per buffer hint. >> > > > > >> > > > > We do have to worry about the CPU cache w.r.t I/O coherency (which is a >> > > > > different hint) and in that case we have all of concerns that Will >> > > > > identified. >> > > > > >> > > > >> > > > For mismatched outer cacheability attributes which Will >> > > > mentioned, I was >> > > > referring to [1] in android kernel. >> > > >> > > I've lost track of the conversation here :/ >> > > >> > > When the GPU has a buffer mapped with IOMMU_LLC, is the buffer also >> > > mapped >> > > into the CPU and with what attributes? Rob said "writecombine for >> > > everything" -- does that mean ioremap_wc() / MEMREMAP_WC? >> > > >> > >> > Rob answered this. >> > >> > > Finally, we need to be careful when we use the word "hint" as >> > > "allocation >> > > hint" has a specific meaning in the architecture, and if we only >> > > mismatch on >> > > those then we're actually ok. But I think IOMMU_LLC is more than >> > > just a >> > > hint, since it actually drives eviction policy (i.e. it enables >> > > writeback). >> > > >> > > Sorry for the pedantry, but I just want to make sure we're all talking >> > > about the same things! >> > > >> > >> > Sorry for the confusion which probably was caused by my mentioning of >> > android, NWA(no write allocate) is an allocation hint which we can >> > ignore >> > for now as it is not introduced yet in upstream. >> > >> >> Any chance of taking this forward? We do not want to miss out on small >> fps >> gain when the product gets released. > > Do we have a solution to the mismatched virtual alias? > Sorry for the long delay on this thread. For mismatched virtual alias question, wasn't this already discussed in stretch when initial support for system cache [1] (which was reverted by you) was added? Excerpt from there, "As seen in downstream kernels there are few non-coherent devices which would not want to allocate in system cache, and therefore would want Inner/Outer non-cached memory. So, we may want to either override the attributes per-device, or as you suggested we may want to introduce another memory type 'sys-cached' that can be added with its separate infra." As for DMA API usage, we do not have any upstream users (video will be one if they decide to upstream that). [1] https://patchwork.kernel.org/project/linux-arm-msm/patch/20180615105329.26800-1-vivek.gautam@codeaurora.org/ Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation