* [PATCH v3 4/6] drm/dp: Add LTTPR helpers
[not found] <20201007170917.1764556-1-imre.deak@intel.com>
@ 2020-10-07 17:09 ` Imre Deak
2020-10-08 16:46 ` [Intel-gfx] " Imre Deak
[not found] ` <160218732911.11034.6649329824047137013@emeril.freedesktop.org>
1 sibling, 1 reply; 4+ messages in thread
From: Imre Deak @ 2020-10-07 17:09 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add the helpers and register definitions needed to read out the common
and per-PHY LTTPR capabilities and perform link training in the LTTPR
non-transparent mode.
v2:
- Add drm_dp_dpcd_read_phy_link_status() and DP_PHY_LTTPR() here instead
of adding these to i915. (Ville)
v3:
- Use memmove() to convert LTTPR to DPRX link status format. (Ville)
Cc: dri-devel@lists.freedesktop.org
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/drm_dp_helper.c | 232 +++++++++++++++++++++++++++++++-
include/drm/drm_dp_helper.h | 62 +++++++++
2 files changed, 290 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 478dd51f738d..79732402336d 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -150,11 +150,8 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
-void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
{
- unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
- DP_TRAINING_AUX_RD_MASK;
-
if (rd_interval > 4)
DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
rd_interval);
@@ -166,8 +163,35 @@ void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
usleep_range(rd_interval, rd_interval * 2);
}
+
+void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK);
+}
EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
+void drm_dp_lttpr_link_train_clock_recovery_delay(void)
+{
+ usleep_range(100, 200);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
+
+static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
+{
+ return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
+}
+
+void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
+{
+ u8 interval = dp_lttpr_phy_cap(phy_cap,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
+ DP_TRAINING_AUX_RD_MASK;
+
+ __drm_dp_link_train_channel_eq_delay(interval);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
+
u8 drm_dp_link_rate_to_bw_code(int link_rate)
{
/* Spec says link_bw = link_rate / 0.27Gbps */
@@ -363,6 +387,59 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
}
EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
+/**
+ * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
+ * @aux: DisplayPort AUX channel
+ * @dp_phy: the DP PHY to get the link status for
+ * @link_status: buffer to return the status in
+ *
+ * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
+ * layout of the returned @link_status matches the DPCD register layout of the
+ * DPRX PHY link status.
+ *
+ * Returns 0 if the information was read successfully or a negative error code
+ * on failure.
+ */
+int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
+ enum drm_dp_phy dp_phy,
+ u8 link_status[DP_LINK_STATUS_SIZE])
+{
+ int ret;
+
+ if (dp_phy == DP_PHY_DPRX) {
+ ret = drm_dp_dpcd_read(aux,
+ DP_LANE0_1_STATUS,
+ link_status,
+ DP_LINK_STATUS_SIZE);
+
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != DP_LINK_STATUS_SIZE);
+
+ return 0;
+ }
+
+ ret = drm_dp_dpcd_read(aux,
+ DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
+ link_status,
+ DP_LINK_STATUS_SIZE - 1);
+
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
+
+ /* Convert the LTTPR to the sink PHY link status layout */
+ memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
+ &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
+ DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
+ link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
+
static bool is_edid_digital_input_dp(const struct edid *edid)
{
return edid && edid->revision >= 4 &&
@@ -2098,6 +2175,153 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
}
EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
+/**
+ * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
+ * @aux: DisplayPort AUX channel
+ * @caps: buffer to return the capability info in
+ *
+ * Read capabilities common to all LTTPRs.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+ int ret;
+
+ ret = drm_dp_dpcd_read(aux,
+ DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
+ caps, DP_LTTPR_COMMON_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
+
+/**
+ * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
+ * @aux: DisplayPort AUX channel
+ * @dp_phy: LTTPR PHY to read the capabilities for
+ * @caps: buffer to return the capability info in
+ *
+ * Read the capabilities for the given LTTPR PHY.
+ *
+ * Returns 0 on success or a negative error code on failure.
+ */
+int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ enum drm_dp_phy dp_phy,
+ u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+ int ret;
+
+ ret = drm_dp_dpcd_read(aux,
+ DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
+ caps, DP_LTTPR_PHY_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
+
+static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
+{
+ return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
+}
+
+/**
+ * drm_dp_lttpr_count - get the number of detected LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Get the number of detected LTTPRs from the LTTPR common capabilities info.
+ *
+ * Returns:
+ * -ERANGE if more than supported number (8) of LTTPRs are detected
+ * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
+ * otherwise the number of detected LTTPRs
+ */
+int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+ u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
+
+ switch (hweight8(count)) {
+ case 0:
+ return 0;
+ case 1:
+ return 8 - ilog2(count);
+ case 8:
+ return -ERANGE;
+ default:
+ return -EINVAL;
+ }
+}
+EXPORT_SYMBOL(drm_dp_lttpr_count);
+
+/**
+ * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Returns the maximum link rate supported by all detected LTTPRs.
+ */
+int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+ u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
+
+ return drm_dp_bw_code_to_link_rate(rate);
+}
+EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
+
+/**
+ * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
+ * @caps: LTTPR common capabilities
+ *
+ * Returns the maximum lane count supported by all detected LTTPRs.
+ */
+int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
+{
+ u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
+
+ return max_lanes & DP_MAX_LANE_COUNT_MASK;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
+
+/**
+ * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
+ * @caps: LTTPR PHY capabilities
+ *
+ * Returns true if the @caps for an LTTPR TX PHY indicate support for
+ * voltage swing level 3.
+ */
+bool
+drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+ u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
+
+ return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
+
+/**
+ * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
+ * @caps: LTTPR PHY capabilities
+ *
+ * Returns true if the @caps for an LTTPR TX PHY indicate support for
+ * pre-emphasis level 3.
+ */
+bool
+drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
+{
+ u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
+
+ return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
+}
+EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
+
/**
* drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
* @aux: DisplayPort AUX channel
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 159191c1ae75..f55a9d1320ca 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1118,15 +1118,58 @@ struct drm_device;
#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
#define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
+
+enum drm_dp_phy {
+ DP_PHY_DPRX,
+
+ DP_PHY_LTTPR1,
+ DP_PHY_LTTPR2,
+ DP_PHY_LTTPR3,
+ DP_PHY_LTTPR4,
+ DP_PHY_LTTPR5,
+ DP_PHY_LTTPR6,
+ DP_PHY_LTTPR7,
+ DP_PHY_LTTPR8,
+
+ DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
+};
+
+#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
+
+#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
+#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
+#define DP_LTTPR_BASE(dp_phy) \
+ (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
+ ((dp_phy) - DP_PHY_LTTPR1))
+
+#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
+ (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
+
#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
+#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
+ DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
+
#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
+#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
+ DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
+
#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
+#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
+ DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
+
#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
+# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
+# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
+
#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
+#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
+ DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
+
#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
+
#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
@@ -1237,9 +1280,13 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ
#define DP_DSC_RECEIVER_CAP_SIZE 0xf
#define EDP_PSR_RECEIVER_CAP_SIZE 2
#define EDP_DISPLAY_CTL_CAP_SIZE 3
+#define DP_LTTPR_COMMON_CAP_SIZE 8
+#define DP_LTTPR_PHY_CAP_SIZE 3
void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void drm_dp_lttpr_link_train_clock_recovery_delay(void);
void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
+void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
u8 drm_dp_link_rate_to_bw_code(int link_rate);
int drm_dp_bw_code_to_link_rate(u8 link_bw);
@@ -1698,6 +1745,10 @@ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
u8 status[DP_LINK_STATUS_SIZE]);
+int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
+ enum drm_dp_phy dp_phy,
+ u8 link_status[DP_LINK_STATUS_SIZE]);
+
bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
u8 real_edid_checksum);
@@ -1747,6 +1798,17 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
const struct drm_dp_desc *desc);
int drm_dp_read_sink_count(struct drm_dp_aux *aux);
+int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
+ u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
+ enum drm_dp_phy dp_phy,
+ u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
+bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
+
void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
void drm_dp_aux_init(struct drm_dp_aux *aux);
int drm_dp_aux_register(struct drm_dp_aux *aux);
--
2.25.1
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/6] drm/dp: Add LTTPR helpers
2020-10-07 17:09 ` [PATCH v3 4/6] drm/dp: Add LTTPR helpers Imre Deak
@ 2020-10-08 16:46 ` Imre Deak
2020-10-08 16:47 ` Lyude Paul
0 siblings, 1 reply; 4+ messages in thread
From: Imre Deak @ 2020-10-08 16:46 UTC (permalink / raw)
To: intel-gfx, Dave Airlie, Lyude Paul, Alex Deucher; +Cc: dri-devel
Hi Dave et all,
On Wed, Oct 07, 2020 at 08:09:15PM +0300, Imre Deak wrote:
> Add the helpers and register definitions needed to read out the common
> and per-PHY LTTPR capabilities and perform link training in the LTTPR
> non-transparent mode.
>
> v2:
> - Add drm_dp_dpcd_read_phy_link_status() and DP_PHY_LTTPR() here instead
> of adding these to i915. (Ville)
> v3:
> - Use memmove() to convert LTTPR to DPRX link status format. (Ville)
>
> Cc: dri-devel@lists.freedesktop.org
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Is it ok to merge this patch via drm-intel-next-queued? If so could
someone Ack it?
Thanks,
Imre
> ---
> drivers/gpu/drm/drm_dp_helper.c | 232 +++++++++++++++++++++++++++++++-
> include/drm/drm_dp_helper.h | 62 +++++++++
> 2 files changed, 290 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 478dd51f738d..79732402336d 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -150,11 +150,8 @@ void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> }
> EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>
> -void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
> {
> - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> - DP_TRAINING_AUX_RD_MASK;
> -
> if (rd_interval > 4)
> DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
> rd_interval);
> @@ -166,8 +163,35 @@ void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>
> usleep_range(rd_interval, rd_interval * 2);
> }
> +
> +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +{
> + __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> + DP_TRAINING_AUX_RD_MASK);
> +}
> EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
>
> +void drm_dp_lttpr_link_train_clock_recovery_delay(void)
> +{
> + usleep_range(100, 200);
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
> +
> +static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
> +{
> + return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
> +}
> +
> +void drm_dp_lttpr_link_train_channel_eq_delay(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
> +{
> + u8 interval = dp_lttpr_phy_cap(phy_cap,
> + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
> + DP_TRAINING_AUX_RD_MASK;
> +
> + __drm_dp_link_train_channel_eq_delay(interval);
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
> +
> u8 drm_dp_link_rate_to_bw_code(int link_rate)
> {
> /* Spec says link_bw = link_rate / 0.27Gbps */
> @@ -363,6 +387,59 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> }
> EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
>
> +/**
> + * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
> + * @aux: DisplayPort AUX channel
> + * @dp_phy: the DP PHY to get the link status for
> + * @link_status: buffer to return the status in
> + *
> + * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
> + * layout of the returned @link_status matches the DPCD register layout of the
> + * DPRX PHY link status.
> + *
> + * Returns 0 if the information was read successfully or a negative error code
> + * on failure.
> + */
> +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
> + enum drm_dp_phy dp_phy,
> + u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> + int ret;
> +
> + if (dp_phy == DP_PHY_DPRX) {
> + ret = drm_dp_dpcd_read(aux,
> + DP_LANE0_1_STATUS,
> + link_status,
> + DP_LINK_STATUS_SIZE);
> +
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != DP_LINK_STATUS_SIZE);
> +
> + return 0;
> + }
> +
> + ret = drm_dp_dpcd_read(aux,
> + DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
> + link_status,
> + DP_LINK_STATUS_SIZE - 1);
> +
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
> +
> + /* Convert the LTTPR to the sink PHY link status layout */
> + memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
> + &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
> + DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
> + link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
> +
> static bool is_edid_digital_input_dp(const struct edid *edid)
> {
> return edid && edid->revision >= 4 &&
> @@ -2098,6 +2175,153 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> }
> EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
>
> +/**
> + * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> + * @aux: DisplayPort AUX channel
> + * @caps: buffer to return the capability info in
> + *
> + * Read capabilities common to all LTTPRs.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + int ret;
> +
> + ret = drm_dp_dpcd_read(aux,
> + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
> + caps, DP_LTTPR_COMMON_CAP_SIZE);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
> +
> +/**
> + * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
> + * @aux: DisplayPort AUX channel
> + * @dp_phy: LTTPR PHY to read the capabilities for
> + * @caps: buffer to return the capability info in
> + *
> + * Read the capabilities for the given LTTPR PHY.
> + *
> + * Returns 0 on success or a negative error code on failure.
> + */
> +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + enum drm_dp_phy dp_phy,
> + u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> +{
> + int ret;
> +
> + ret = drm_dp_dpcd_read(aux,
> + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> + caps, DP_LTTPR_PHY_CAP_SIZE);
> + if (ret < 0)
> + return ret;
> +
> + WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
> +
> +static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
> +{
> + return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> +}
> +
> +/**
> + * drm_dp_lttpr_count - get the number of detected LTTPRs
> + * @caps: LTTPR common capabilities
> + *
> + * Get the number of detected LTTPRs from the LTTPR common capabilities info.
> + *
> + * Returns:
> + * -ERANGE if more than supported number (8) of LTTPRs are detected
> + * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
> + * otherwise the number of detected LTTPRs
> + */
> +int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
> +
> + switch (hweight8(count)) {
> + case 0:
> + return 0;
> + case 1:
> + return 8 - ilog2(count);
> + case 8:
> + return -ERANGE;
> + default:
> + return -EINVAL;
> + }
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_count);
> +
> +/**
> + * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
> + * @caps: LTTPR common capabilities
> + *
> + * Returns the maximum link rate supported by all detected LTTPRs.
> + */
> +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
> +
> + return drm_dp_bw_code_to_link_rate(rate);
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
> +
> +/**
> + * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
> + * @caps: LTTPR common capabilities
> + *
> + * Returns the maximum lane count supported by all detected LTTPRs.
> + */
> +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> +{
> + u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
> +
> + return max_lanes & DP_MAX_LANE_COUNT_MASK;
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
> +
> +/**
> + * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
> + * @caps: LTTPR PHY capabilities
> + *
> + * Returns true if the @caps for an LTTPR TX PHY indicate support for
> + * voltage swing level 3.
> + */
> +bool
> +drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> +{
> + u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
> +
> + return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
> +
> +/**
> + * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
> + * @caps: LTTPR PHY capabilities
> + *
> + * Returns true if the @caps for an LTTPR TX PHY indicate support for
> + * pre-emphasis level 3.
> + */
> +bool
> +drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> +{
> + u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
> +
> + return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
> +}
> +EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
> +
> /**
> * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> * @aux: DisplayPort AUX channel
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 159191c1ae75..f55a9d1320ca 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1118,15 +1118,58 @@ struct drm_device;
> #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */
> #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */
> +
> +enum drm_dp_phy {
> + DP_PHY_DPRX,
> +
> + DP_PHY_LTTPR1,
> + DP_PHY_LTTPR2,
> + DP_PHY_LTTPR3,
> + DP_PHY_LTTPR4,
> + DP_PHY_LTTPR5,
> + DP_PHY_LTTPR6,
> + DP_PHY_LTTPR7,
> + DP_PHY_LTTPR8,
> +
> + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
> +};
> +
> +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i))
> +
> +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
> +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
> +#define DP_LTTPR_BASE(dp_phy) \
> + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
> + ((dp_phy) - DP_PHY_LTTPR1))
> +
> +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
> + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
> +
> #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */
> +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
> + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
> +
> #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */
> +#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
> + DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
> +
> #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /* 1.3 */
> #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /* 1.3 */
> #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /* 1.3 */
> #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
> +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
> + DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
> +
> #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /* 1.4a */
> +# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
> +# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
> +
> #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */
> +#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
> + DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
> +
> #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /* 1.3 */
> +
> #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
> #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */
> #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /* 1.3 */
> @@ -1237,9 +1280,13 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZ
> #define DP_DSC_RECEIVER_CAP_SIZE 0xf
> #define EDP_PSR_RECEIVER_CAP_SIZE 2
> #define EDP_DISPLAY_CTL_CAP_SIZE 3
> +#define DP_LTTPR_COMMON_CAP_SIZE 8
> +#define DP_LTTPR_PHY_CAP_SIZE 3
>
> void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> +void drm_dp_lttpr_link_train_clock_recovery_delay(void);
> void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> +void drm_dp_lttpr_link_train_channel_eq_delay(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
>
> u8 drm_dp_link_rate_to_bw_code(int link_rate);
> int drm_dp_bw_code_to_link_rate(u8 link_bw);
> @@ -1698,6 +1745,10 @@ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
> int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> u8 status[DP_LINK_STATUS_SIZE]);
>
> +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
> + enum drm_dp_phy dp_phy,
> + u8 link_status[DP_LINK_STATUS_SIZE]);
> +
> bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
> u8 real_edid_checksum);
>
> @@ -1747,6 +1798,17 @@ bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
> const struct drm_dp_desc *desc);
> int drm_dp_read_sink_count(struct drm_dp_aux *aux);
>
> +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> + enum drm_dp_phy dp_phy,
> + u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> +int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
> +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> +bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> +bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> +
> void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
> void drm_dp_aux_init(struct drm_dp_aux *aux);
> int drm_dp_aux_register(struct drm_dp_aux *aux);
> --
> 2.25.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH v3 4/6] drm/dp: Add LTTPR helpers
2020-10-08 16:46 ` [Intel-gfx] " Imre Deak
@ 2020-10-08 16:47 ` Lyude Paul
0 siblings, 0 replies; 4+ messages in thread
From: Lyude Paul @ 2020-10-08 16:47 UTC (permalink / raw)
To: imre.deak, intel-gfx, Dave Airlie, Alex Deucher; +Cc: dri-devel
Acked-by: Lyude Paul <lyude@redhat.com>
On Thu, 2020-10-08 at 19:46 +0300, Imre Deak wrote:
> Hi Dave et all,
>
> On Wed, Oct 07, 2020 at 08:09:15PM +0300, Imre Deak wrote:
> > Add the helpers and register definitions needed to read out the common
> > and per-PHY LTTPR capabilities and perform link training in the LTTPR
> > non-transparent mode.
> >
> > v2:
> > - Add drm_dp_dpcd_read_phy_link_status() and DP_PHY_LTTPR() here instead
> > of adding these to i915. (Ville)
> > v3:
> > - Use memmove() to convert LTTPR to DPRX link status format. (Ville)
> >
> > Cc: dri-devel@lists.freedesktop.org
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Is it ok to merge this patch via drm-intel-next-queued? If so could
> someone Ack it?
>
> Thanks,
> Imre
>
> > ---
> > drivers/gpu/drm/drm_dp_helper.c | 232 +++++++++++++++++++++++++++++++-
> > include/drm/drm_dp_helper.h | 62 +++++++++
> > 2 files changed, 290 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/drm_dp_helper.c
> > b/drivers/gpu/drm/drm_dp_helper.c
> > index 478dd51f738d..79732402336d 100644
> > --- a/drivers/gpu/drm/drm_dp_helper.c
> > +++ b/drivers/gpu/drm/drm_dp_helper.c
> > @@ -150,11 +150,8 @@ void drm_dp_link_train_clock_recovery_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > }
> > EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
> >
> > -void drm_dp_link_train_channel_eq_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > +static void __drm_dp_link_train_channel_eq_delay(unsigned long rd_interval)
> > {
> > - unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > - DP_TRAINING_AUX_RD_MASK;
> > -
> > if (rd_interval > 4)
> > DRM_DEBUG_KMS("AUX interval %lu, out of range (max 4)\n",
> > rd_interval);
> > @@ -166,8 +163,35 @@ void drm_dp_link_train_channel_eq_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> >
> > usleep_range(rd_interval, rd_interval * 2);
> > }
> > +
> > +void drm_dp_link_train_channel_eq_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE])
> > +{
> > + __drm_dp_link_train_channel_eq_delay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > + DP_TRAINING_AUX_RD_MASK);
> > +}
> > EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
> >
> > +void drm_dp_lttpr_link_train_clock_recovery_delay(void)
> > +{
> > + usleep_range(100, 200);
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
> > +
> > +static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
> > +{
> > + return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
> > +}
> > +
> > +void drm_dp_lttpr_link_train_channel_eq_delay(const u8
> > phy_cap[DP_LTTPR_PHY_CAP_SIZE])
> > +{
> > + u8 interval = dp_lttpr_phy_cap(phy_cap,
> > + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1
> > ) &
> > + DP_TRAINING_AUX_RD_MASK;
> > +
> > + __drm_dp_link_train_channel_eq_delay(interval);
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
> > +
> > u8 drm_dp_link_rate_to_bw_code(int link_rate)
> > {
> > /* Spec says link_bw = link_rate / 0.27Gbps */
> > @@ -363,6 +387,59 @@ int drm_dp_dpcd_read_link_status(struct drm_dp_aux
> > *aux,
> > }
> > EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
> >
> > +/**
> > + * drm_dp_dpcd_read_phy_link_status - get the link status information for a
> > DP PHY
> > + * @aux: DisplayPort AUX channel
> > + * @dp_phy: the DP PHY to get the link status for
> > + * @link_status: buffer to return the status in
> > + *
> > + * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status.
> > The
> > + * layout of the returned @link_status matches the DPCD register layout of
> > the
> > + * DPRX PHY link status.
> > + *
> > + * Returns 0 if the information was read successfully or a negative error
> > code
> > + * on failure.
> > + */
> > +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
> > + enum drm_dp_phy dp_phy,
> > + u8 link_status[DP_LINK_STATUS_SIZE])
> > +{
> > + int ret;
> > +
> > + if (dp_phy == DP_PHY_DPRX) {
> > + ret = drm_dp_dpcd_read(aux,
> > + DP_LANE0_1_STATUS,
> > + link_status,
> > + DP_LINK_STATUS_SIZE);
> > +
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != DP_LINK_STATUS_SIZE);
> > +
> > + return 0;
> > + }
> > +
> > + ret = drm_dp_dpcd_read(aux,
> > + DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
> > + link_status,
> > + DP_LINK_STATUS_SIZE - 1);
> > +
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
> > +
> > + /* Convert the LTTPR to the sink PHY link status layout */
> > + memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
> > + &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
> > + DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
> > + link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
> > +
> > static bool is_edid_digital_input_dp(const struct edid *edid)
> > {
> > return edid && edid->revision >= 4 &&
> > @@ -2098,6 +2175,153 @@ int drm_dp_dsc_sink_supported_input_bpcs(const u8
> > dsc_dpcd[DP_DSC_RECEIVER_CAP_S
> > }
> > EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
> >
> > +/**
> > + * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
> > + * @aux: DisplayPort AUX channel
> > + * @caps: buffer to return the capability info in
> > + *
> > + * Read capabilities common to all LTTPRs.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> > + u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> > +{
> > + int ret;
> > +
> > + ret = drm_dp_dpcd_read(aux,
> > + DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_R
> > EV,
> > + caps, DP_LTTPR_COMMON_CAP_SIZE);
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
> > +
> > +/**
> > + * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
> > + * @aux: DisplayPort AUX channel
> > + * @dp_phy: LTTPR PHY to read the capabilities for
> > + * @caps: buffer to return the capability info in
> > + *
> > + * Read the capabilities for the given LTTPR PHY.
> > + *
> > + * Returns 0 on success or a negative error code on failure.
> > + */
> > +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> > + enum drm_dp_phy dp_phy,
> > + u8 caps[DP_LTTPR_PHY_CAP_SIZE])
> > +{
> > + int ret;
> > +
> > + ret = drm_dp_dpcd_read(aux,
> > + DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
> > + caps, DP_LTTPR_PHY_CAP_SIZE);
> > + if (ret < 0)
> > + return ret;
> > +
> > + WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
> > +
> > +static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int
> > r)
> > +{
> > + return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
> > +}
> > +
> > +/**
> > + * drm_dp_lttpr_count - get the number of detected LTTPRs
> > + * @caps: LTTPR common capabilities
> > + *
> > + * Get the number of detected LTTPRs from the LTTPR common capabilities
> > info.
> > + *
> > + * Returns:
> > + * -ERANGE if more than supported number (8) of LTTPRs are detected
> > + * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
> > + * otherwise the number of detected LTTPRs
> > + */
> > +int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> > +{
> > + u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
> > +
> > + switch (hweight8(count)) {
> > + case 0:
> > + return 0;
> > + case 1:
> > + return 8 - ilog2(count);
> > + case 8:
> > + return -ERANGE;
> > + default:
> > + return -EINVAL;
> > + }
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_count);
> > +
> > +/**
> > + * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all
> > LTTPRs
> > + * @caps: LTTPR common capabilities
> > + *
> > + * Returns the maximum link rate supported by all detected LTTPRs.
> > + */
> > +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> > +{
> > + u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
> > +
> > + return drm_dp_bw_code_to_link_rate(rate);
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
> > +
> > +/**
> > + * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by
> > all LTTPRs
> > + * @caps: LTTPR common capabilities
> > + *
> > + * Returns the maximum lane count supported by all detected LTTPRs.
> > + */
> > +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
> > +{
> > + u8 max_lanes = dp_lttpr_common_cap(caps,
> > DP_MAX_LANE_COUNT_PHY_REPEATER);
> > +
> > + return max_lanes & DP_MAX_LANE_COUNT_MASK;
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
> > +
> > +/**
> > + * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3
> > support
> > + * @caps: LTTPR PHY capabilities
> > + *
> > + * Returns true if the @caps for an LTTPR TX PHY indicate support for
> > + * voltage swing level 3.
> > + */
> > +bool
> > +drm_dp_lttpr_voltage_swing_level_3_supported(const u8
> > caps[DP_LTTPR_PHY_CAP_SIZE])
> > +{
> > + u8 txcap = dp_lttpr_phy_cap(caps,
> > DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
> > +
> > + return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
> > +
> > +/**
> > + * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3
> > support
> > + * @caps: LTTPR PHY capabilities
> > + *
> > + * Returns true if the @caps for an LTTPR TX PHY indicate support for
> > + * pre-emphasis level 3.
> > + */
> > +bool
> > +drm_dp_lttpr_pre_emphasis_level_3_supported(const u8
> > caps[DP_LTTPR_PHY_CAP_SIZE])
> > +{
> > + u8 txcap = dp_lttpr_phy_cap(caps,
> > DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
> > +
> > + return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
> > +}
> > +EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
> > +
> > /**
> > * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
> > * @aux: DisplayPort AUX channel
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 159191c1ae75..f55a9d1320ca 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -1118,15 +1118,58 @@ struct drm_device;
> > #define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /*
> > 1.4a */
> > #define DP_Repeater_FEC_CAPABILITY 0xf0004 /* 1.4 */
> > #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /*
> > 1.4a */
> > +
> > +enum drm_dp_phy {
> > + DP_PHY_DPRX,
> > +
> > + DP_PHY_LTTPR1,
> > + DP_PHY_LTTPR2,
> > + DP_PHY_LTTPR3,
> > + DP_PHY_LTTPR4,
> > + DP_PHY_LTTPR5,
> > + DP_PHY_LTTPR6,
> > + DP_PHY_LTTPR7,
> > + DP_PHY_LTTPR8,
> > +
> > + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8,
> > +};
> > +
> > +#define DP_PHY_LTTPR(i) (DP_PHY_LTTP
> > R1 + (i))
> > +
> > +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */
> > +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */
> > +#define DP_LTTPR_BASE(dp_phy) \
> > + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \
> > + ((dp_phy) - DP_PHY_LTTPR1))
> > +
> > +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \
> > + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg))
> > +
> > #define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /*
> > 1.3 */
> > +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \
> > + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1)
> > +
> > #define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /*
> > 1.3 */
> > +#define DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy) \
> > + DP_LTTPR_REG(dp_phy, DP_TRAINING_LANE0_SET_PHY_REPEATER1)
> > +
> > #define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012 /*
> > 1.3 */
> > #define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013 /*
> > 1.3 */
> > #define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014 /*
> > 1.3 */
> > #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */
> > +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy) \
> > + DP_LTTPR_REG(dp_phy, DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1)
> > +
> > #define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021 /*
> > 1.4a */
> > +# define DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED BIT(0)
> > +# define DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED BIT(1)
> > +
> > #define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /*
> > 1.3 */
> > +#define DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy) \
> > + DP_LTTPR_REG(dp_phy, DP_LANE0_1_STATUS_PHY_REPEATER1)
> > +
> > #define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031 /*
> > 1.3 */
> > +
> > #define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032 /* 1.3 */
> > #define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /*
> > 1.3 */
> > #define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034 /*
> > 1.3 */
> > @@ -1237,9 +1280,13 @@ u8 drm_dp_get_adjust_request_post_cursor(const u8
> > link_status[DP_LINK_STATUS_SIZ
> > #define DP_DSC_RECEIVER_CAP_SIZE 0xf
> > #define EDP_PSR_RECEIVER_CAP_SIZE 2
> > #define EDP_DISPLAY_CTL_CAP_SIZE 3
> > +#define DP_LTTPR_COMMON_CAP_SIZE 8
> > +#define DP_LTTPR_PHY_CAP_SIZE 3
> >
> > void drm_dp_link_train_clock_recovery_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE]);
> > +void drm_dp_lttpr_link_train_clock_recovery_delay(void);
> > void drm_dp_link_train_channel_eq_delay(const u8
> > dpcd[DP_RECEIVER_CAP_SIZE]);
> > +void drm_dp_lttpr_link_train_channel_eq_delay(const u8
> > caps[DP_LTTPR_PHY_CAP_SIZE]);
> >
> > u8 drm_dp_link_rate_to_bw_code(int link_rate);
> > int drm_dp_bw_code_to_link_rate(u8 link_bw);
> > @@ -1698,6 +1745,10 @@ int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
> > int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
> > u8 status[DP_LINK_STATUS_SIZE]);
> >
> > +int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
> > + enum drm_dp_phy dp_phy,
> > + u8 link_status[DP_LINK_STATUS_SIZE]);
> > +
> > bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
> > u8 real_edid_checksum);
> >
> > @@ -1747,6 +1798,17 @@ bool drm_dp_read_sink_count_cap(struct drm_connector
> > *connector,
> > const struct drm_dp_desc *desc);
> > int drm_dp_read_sink_count(struct drm_dp_aux *aux);
> >
> > +int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
> > + u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> > +int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
> > + enum drm_dp_phy dp_phy,
> > + u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
> > +int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
> > +int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> > +int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
> > +bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8
> > caps[DP_LTTPR_PHY_CAP_SIZE]);
> > +bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8
> > caps[DP_LTTPR_PHY_CAP_SIZE]);
> > +
> > void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
> > void drm_dp_aux_init(struct drm_dp_aux *aux);
> > int drm_dp_aux_register(struct drm_dp_aux *aux);
> > --
> > 2.25.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Sincerely,
Lyude Paul (she/her)
Software Engineer at Red Hat
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: ✓ Fi.CI.IGT: success for rm/i915: Add support for LTTPR non-transparent link training mode (rev2)
[not found] ` <160218732911.11034.6649329824047137013@emeril.freedesktop.org>
@ 2020-10-12 13:05 ` Imre Deak
0 siblings, 0 replies; 4+ messages in thread
From: Imre Deak @ 2020-10-12 13:05 UTC (permalink / raw)
To: intel-gfx, Ville Syrjälä, Lyude Paul, Daniel Vetter; +Cc: dri-devel
On Thu, Oct 08, 2020 at 08:02:09PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: rm/i915: Add support for LTTPR non-transparent link training mode (rev2)
> URL : https://patchwork.freedesktop.org/series/82449/
> State : success
Thanks for the reviews, patchset is pushed to -dinq.
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_9113_full -> Patchwork_18658_full
> ====================================================
>
> Summary
> -------
>
> **SUCCESS**
>
> No regressions found.
>
>
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_18658_full:
>
> ### IGT changes ###
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * {igt@gem_exec_capture@pi@vcs0}:
> - shard-skl: NOTRUN -> [INCOMPLETE][1]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl9/igt@gem_exec_capture@pi@vcs0.html
>
>
> Known issues
> ------------
>
> Here are the changes found in Patchwork_18658_full that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@gem_exec_suspend@basic-s0:
> - shard-iclb: [PASS][2] -> [INCOMPLETE][3] ([i915#1090] / [i915#1185])
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb2/igt@gem_exec_suspend@basic-s0.html
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-iclb3/igt@gem_exec_suspend@basic-s0.html
>
> * igt@gem_huc_copy@huc-copy:
> - shard-tglb: [PASS][4] -> [SKIP][5] ([i915#2190])
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb7/igt@gem_huc_copy@huc-copy.html
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-tglb6/igt@gem_huc_copy@huc-copy.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@wc:
> - shard-hsw: [PASS][6] -> [FAIL][7] ([i915#1888]) +1 similar issue
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@wc.html
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@wc.html
>
> * igt@i915_pm_dc@dc6-psr:
> - shard-skl: [PASS][8] -> [FAIL][9] ([i915#454])
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl7/igt@i915_pm_dc@dc6-psr.html
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl10/igt@i915_pm_dc@dc6-psr.html
>
> * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
> - shard-hsw: [PASS][10] -> [FAIL][11] ([i915#2370])
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw2/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw8/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
>
> * igt@kms_draw_crc@draw-method-rgb565-render-untiled:
> - shard-skl: [PASS][12] -> [FAIL][13] ([i915#52] / [i915#54])
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
>
> * igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled:
> - shard-snb: [PASS][14] -> [SKIP][15] ([fdo#109271])
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-snb4/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-snb2/igt@kms_draw_crc@draw-method-xrgb2101010-pwrite-untiled.html
>
> * igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1:
> - shard-kbl: [PASS][16] -> [DMESG-WARN][17] ([i915#1982]) +1 similar issue
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl1/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1.html
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-kbl6/igt@kms_flip@flip-vs-blocking-wf-vblank@a-dp1.html
>
> * igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1:
> - shard-skl: [PASS][18] -> [DMESG-WARN][19] ([i915#1982]) +5 similar issues
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl5/igt@kms_flip@flip-vs-blocking-wf-vblank@a-edp1.html
>
> * igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
> - shard-skl: [PASS][20] -> [FAIL][21] ([i915#79])
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
> [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
>
> * igt@kms_flip@flip-vs-suspend@a-dp1:
> - shard-kbl: [PASS][22] -> [INCOMPLETE][23] ([i915#155])
> [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl7/igt@kms_flip@flip-vs-suspend@a-dp1.html
> [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-kbl1/igt@kms_flip@flip-vs-suspend@a-dp1.html
>
> * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
> - shard-hsw: [PASS][24] -> [INCOMPLETE][25] ([i915#2055])
> [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
> [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw6/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-stridechange:
> - shard-glk: [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) +1 similar issue
> [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
> [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-glk6/igt@kms_frontbuffer_tracking@fbc-stridechange.html
>
> * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
> - shard-tglb: [PASS][28] -> [DMESG-WARN][29] ([i915#1982]) +1 similar issue
> [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
> [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html
>
> * igt@kms_hdr@bpc-switch-suspend:
> - shard-skl: [PASS][30] -> [FAIL][31] ([i915#1188]) +1 similar issue
> [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
> [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
>
> * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
> - shard-skl: [PASS][32] -> [FAIL][33] ([fdo#108145] / [i915#265]) +2 similar issues
> [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
> [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
>
> * igt@kms_psr@psr2_cursor_plane_move:
> - shard-iclb: [PASS][34] -> [SKIP][35] ([fdo#109441])
> [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
> [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-iclb8/igt@kms_psr@psr2_cursor_plane_move.html
>
> * igt@kms_setmode@basic:
> - shard-glk: [PASS][36] -> [FAIL][37] ([i915#31])
> [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk4/igt@kms_setmode@basic.html
> [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-glk5/igt@kms_setmode@basic.html
>
>
> #### Possible fixes ####
>
> * {igt@gem_exec_capture@pi@rcs0}:
> - shard-skl: [INCOMPLETE][38] -> [PASS][39]
> [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl2/igt@gem_exec_capture@pi@rcs0.html
> [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl9/igt@gem_exec_capture@pi@rcs0.html
>
> * igt@gem_mmap_gtt@basic-small-bo:
> - shard-hsw: [INCOMPLETE][40] -> [PASS][41]
> [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw2/igt@gem_mmap_gtt@basic-small-bo.html
> [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw1/igt@gem_mmap_gtt@basic-small-bo.html
>
> * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt:
> - shard-hsw: [FAIL][42] ([i915#1888]) -> [PASS][43]
> [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw8/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt.html
> [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup@gtt.html
>
> * igt@i915_pm_rpm@system-suspend:
> - shard-skl: [INCOMPLETE][44] ([i915#151]) -> [PASS][45]
> [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl1/igt@i915_pm_rpm@system-suspend.html
> [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl2/igt@i915_pm_rpm@system-suspend.html
>
> * igt@i915_selftest@live@gt_heartbeat:
> - shard-skl: [DMESG-FAIL][46] ([i915#541]) -> [PASS][47]
> [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html
> [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl3/igt@i915_selftest@live@gt_heartbeat.html
>
> * {igt@kms_async_flips@alternate-sync-async-flip}:
> - shard-kbl: [FAIL][48] ([i915#2521]) -> [PASS][49]
> [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-kbl2/igt@kms_async_flips@alternate-sync-async-flip.html
> [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-kbl2/igt@kms_async_flips@alternate-sync-async-flip.html
>
> * {igt@kms_async_flips@async-flip-with-page-flip-events}:
> - shard-glk: [FAIL][50] ([i915#2521]) -> [PASS][51]
> [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk3/igt@kms_async_flips@async-flip-with-page-flip-events.html
> [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-glk3/igt@kms_async_flips@async-flip-with-page-flip-events.html
>
> * igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge:
> - shard-glk: [DMESG-WARN][52] ([i915#1982]) -> [PASS][53]
> [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk1/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
> [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-glk9/igt@kms_cursor_edge_walk@pipe-b-128x128-bottom-edge.html
>
> * igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1:
> - shard-hsw: [DMESG-WARN][54] ([i915#1982]) -> [PASS][55]
> [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-hsw6/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
> [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-hsw8/igt@kms_flip@2x-dpms-vs-vblank-race@ab-vga1-hdmi-a1.html
>
> * igt@kms_frontbuffer_tracking@fbc-farfromfence:
> - shard-glk: [FAIL][56] ([i915#49]) -> [PASS][57]
> [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-glk8/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
> [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-glk4/igt@kms_frontbuffer_tracking@fbc-farfromfence.html
>
> * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render:
> - shard-skl: [FAIL][58] ([i915#49]) -> [PASS][59]
> [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
> [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-render.html
>
> * igt@kms_plane@plane-position-covered-pipe-b-planes:
> - shard-skl: [DMESG-WARN][60] ([i915#1982]) -> [PASS][61] +4 similar issues
> [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl8/igt@kms_plane@plane-position-covered-pipe-b-planes.html
> [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl8/igt@kms_plane@plane-position-covered-pipe-b-planes.html
>
> * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
> - shard-skl: [FAIL][62] ([fdo#108145] / [i915#265]) -> [PASS][63]
> [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
> [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
>
> * igt@kms_psr@psr2_primary_mmap_cpu:
> - shard-iclb: [SKIP][64] ([fdo#109441]) -> [PASS][65] +3 similar issues
> [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html
> [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
>
> * igt@kms_setmode@basic:
> - shard-skl: [FAIL][66] ([i915#31]) -> [PASS][67]
> [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-skl5/igt@kms_setmode@basic.html
> [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-skl2/igt@kms_setmode@basic.html
>
> * igt@prime_vgem@sync@rcs0:
> - shard-iclb: [INCOMPLETE][68] ([i915#409]) -> [PASS][69]
> [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb3/igt@prime_vgem@sync@rcs0.html
> [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-iclb4/igt@prime_vgem@sync@rcs0.html
>
>
> #### Warnings ####
>
> * igt@i915_pm_dc@dc3co-vpb-simulation:
> - shard-iclb: [SKIP][70] ([i915#658]) -> [SKIP][71] ([i915#588])
> [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
> [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
>
> * igt@i915_pm_dc@dc5-psr:
> - shard-tglb: [DMESG-WARN][72] ([i915#2411]) -> [FAIL][73] ([i915#1899])
> [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9113/shard-tglb6/igt@i915_pm_dc@dc5-psr.html
> [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/shard-tglb5/igt@i915_pm_dc@dc5-psr.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
> [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
> [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
> [i915#1090]: https://gitlab.freedesktop.org/drm/intel/issues/1090
> [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
> [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
> [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
> [i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
> [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
> [i915#1899]: https://gitlab.freedesktop.org/drm/intel/issues/1899
> [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
> [i915#2055]: https://gitlab.freedesktop.org/drm/intel/issues/2055
> [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
> [i915#2370]: https://gitlab.freedesktop.org/drm/intel/issues/2370
> [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
> [i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
> [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
> [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
> [i915#409]: https://gitlab.freedesktop.org/drm/intel/issues/409
> [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
> [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
> [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
> [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
> [i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
> [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
> [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
> [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
>
>
> Participating hosts (11 -> 11)
> ------------------------------
>
> No changes in participating hosts
>
>
> Build changes
> -------------
>
> * Linux: CI_DRM_9113 -> Patchwork_18658
>
> CI-20190529: 20190529
> CI_DRM_9113: 412ff15f2b9a97bd0ab32f562ecb7efc84837881 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGT_5805: 9ce50ffed89a46fa1bc98ee2cfe2271c49801079 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> Patchwork_18658: 85eaa572264dad0d1a125c38307cc18d55497c6d @ git://anongit.freedesktop.org/gfx-ci/linux
> piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18658/index.html
_______________________________________________
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end of thread, other threads:[~2020-10-12 13:08 UTC | newest]
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[not found] <20201007170917.1764556-1-imre.deak@intel.com>
2020-10-07 17:09 ` [PATCH v3 4/6] drm/dp: Add LTTPR helpers Imre Deak
2020-10-08 16:46 ` [Intel-gfx] " Imre Deak
2020-10-08 16:47 ` Lyude Paul
[not found] ` <160218732911.11034.6649329824047137013@emeril.freedesktop.org>
2020-10-12 13:05 ` ✓ Fi.CI.IGT: success for rm/i915: Add support for LTTPR non-transparent link training mode (rev2) Imre Deak
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