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[79.139.176.16]) by smtp.googlemail.com with ESMTPSA id u15sm401868lji.21.2021.10.14.17.43.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Oct 2021 17:43:50 -0700 (PDT) Subject: Re: [PATCH v12 05/35] dt-bindings: clock: tegra-car: Document new clock sub-nodes To: Stephen Boyd , Adrian Hunter , Jonathan Hunter , Lee Jones , Michael Turquette , Mikko Perttunen , Nishanth Menon , Peter Chen , Peter De Schrijver , Rob Herring , Thierry Reding , Ulf Hansson , =?UTF-8?Q?Uwe_Kleine-K=c3=b6nig?= , Viresh Kumar Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-usb@vger.kernel.org, linux-staging@lists.linux.dev, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, Mark Brown , Vignesh Raghavendra , Richard Weinberger , Miquel Raynal , Lucas Stach , Stefan Agner , Mauro Carvalho Chehab , David Heidelberg References: <20210920181145.19543-1-digetx@gmail.com> <20210920181145.19543-6-digetx@gmail.com> <163425700766.1688384.4481739110941660602@swboyd.mtv.corp.google.com> From: Dmitry Osipenko Message-ID: <4090acf8-c8af-d98c-2121-9fd105365e55@gmail.com> Date: Fri, 15 Oct 2021 03:43:49 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <163425700766.1688384.4481739110941660602@swboyd.mtv.corp.google.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 15.10.2021 03:16, Stephen Boyd пишет: > Quoting Dmitry Osipenko (2021-09-20 11:11:15) >> diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml >> index 459d2a525393..f832abb7f11a 100644 >> --- a/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml >> +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml >> @@ -42,6 +42,36 @@ properties: >> "#reset-cells": >> const: 1 >> >> +patternProperties: >> + "^(sclk)|(pll-[cem])$": >> + type: object >> + properties: >> + compatible: >> + enum: >> + - nvidia,tegra20-sclk >> + - nvidia,tegra30-sclk >> + - nvidia,tegra30-pllc >> + - nvidia,tegra30-plle >> + - nvidia,tegra30-pllm >> + >> + operating-points-v2: true >> + >> + clocks: >> + items: >> + - description: node's clock >> + >> + power-domains: >> + maxItems: 1 >> + description: phandle to the core SoC power domain > > Is this done to associate the power domain with a particular clk? And an > OPP table with a particular clk? Yes