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From: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
To: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
	dri-devel@lists.freedesktop.org
Cc: linux-renesas-soc@vger.kernel.org,
	Kieran Bingham <kieran.bingham@ideasonboard.com>
Subject: Re: [PATCH 1/2] drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3
Date: Wed, 22 Feb 2023 10:07:10 +0200	[thread overview]
Message-ID: <43324903-96e2-29ef-5a38-01cee2d4b0f0@ideasonboard.com> (raw)
In-Reply-To: <20230222050623.29080-2-laurent.pinchart+renesas@ideasonboard.com>

On 22/02/2023 07:06, Laurent Pinchart wrote:
> The ESCR and OTAR registers are not present in all DU channels on Gen3
> SoCs. ESCR only exists in channels that can be routed to an LVDS or
> DPAD, and OTAR in channels that can be routed to a DPAD. Skip writing
> those registers for other channels. This replaces the DU gen check, as
> Gen4 doesn't have LVDS or DPAD outputs.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> ---
>   drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 17 +++++++++++++++--
>   1 file changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 5e552b326162..d6d29be6b4f4 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -298,12 +298,25 @@ static void rcar_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
>   		escr = params.escr;
>   	}
>   
> -	if (rcdu->info->gen < 4) {
> +	/*
> +	 * The ESCR register only exists in DU channels that can output to an
> +	 * LVDS or DPAT, and the OTAR register in DU channels that can output
> +	 * to a DPAD.
> +	 */
> +	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_LVDS1].possible_crtcs) &
> +	    BIT(rcrtc->index)) {
>   		dev_dbg(rcrtc->dev->dev, "%s: ESCR 0x%08x\n", __func__, escr);
>   
>   		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? ESCR13 : ESCR02, escr);
> +	}
> +
> +	if ((rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs |
> +	     rcdu->info->routes[RCAR_DU_OUTPUT_DPAD1].possible_crtcs) &
> +	    BIT(rcrtc->index))
>   		rcar_du_crtc_write(rcrtc, rcrtc->index % 2 ? OTAR13 : OTAR02, 0);
> -	}
>   
>   	/* Signal polarities */
>   	dsmr = ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DSMR_VSL : 0)

Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>

  Tomi


  reply	other threads:[~2023-02-22  8:07 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-02-22  5:06 [PATCH 0/2] drm: rcar-du: Avoid writing reserved register fields Laurent Pinchart
2023-02-22  5:06 ` [PATCH 1/2] drm: rcar-du: Don't write unimplemented ESCR and OTAR registers on Gen3 Laurent Pinchart
2023-02-22  8:07   ` Tomi Valkeinen [this message]
2023-02-22  5:06 ` [PATCH 2/2] drm: rcar-du: Disable alpha blending for DU planes used with VSP Laurent Pinchart
2023-02-22  7:39   ` Tomi Valkeinen

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