From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Andi Shyti" <andi.shyti@linux.intel.com>,
"Tvrtko Ursulin" <tvrtko.ursulin@intel.com>,
"David Airlie" <airlied@linux.ie>,
dri-devel@lists.freedesktop.org,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
linux-kernel@vger.kernel.org,
"Chris Wilson" <chris.p.wilson@intel.com>,
"Daniele Ceraolo Spurio" <daniele.ceraolospurio@intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Dave Airlie" <airlied@redhat.com>,
stable@vger.kernel.org,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
intel-gfx@lists.freedesktop.org, "Fei Yang" <fei.yang@intel.com>
Subject: [PATCH v3 3/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations
Date: Wed, 27 Jul 2022 14:29:53 +0200 [thread overview]
Message-ID: <59724d9f5cf1e93b1620d01b8332ac991555283d.1658924372.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1658924372.git.mchehab@kernel.org>
From: Chris Wilson <chris.p.wilson@intel.com>
Ensure that the TLB of the OA unit is also invalidated
on gen12 HW, as just invalidating the TLB of an engine is not
enough.
Cc: stable@vger.kernel.org
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---
To avoid mailbombing on a large number of people, only mailing lists were C/C on the cover.
See [PATCH v3 0/6] at: https://lore.kernel.org/all/cover.1658924372.git.mchehab@kernel.org/
drivers/gpu/drm/i915/gt/intel_gt.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index c4d43da84d8e..1d84418e8676 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -11,6 +11,7 @@
#include "pxp/intel_pxp.h"
#include "i915_drv.h"
+#include "i915_perf_oa_regs.h"
#include "intel_context.h"
#include "intel_engine_pm.h"
#include "intel_engine_regs.h"
@@ -969,6 +970,15 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt)
awake |= engine->mask;
}
+ /* Wa_2207587034:tgl,dg1,rkl,adl-s,adl-p */
+ if (awake &&
+ (IS_TIGERLAKE(i915) ||
+ IS_DG1(i915) ||
+ IS_ROCKETLAKE(i915) ||
+ IS_ALDERLAKE_S(i915) ||
+ IS_ALDERLAKE_P(i915)))
+ intel_uncore_write_fw(uncore, GEN12_OA_TLB_INV_CR, 1);
+
spin_unlock_irq(&uncore->lock);
for_each_engine_masked(engine, gt, awake, tmp) {
--
2.36.1
next prev parent reply other threads:[~2022-07-27 12:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-27 12:29 [PATCH v3 0/6] drm/i915: reduce TLB performance regressions Mauro Carvalho Chehab
2022-07-27 12:29 ` [PATCH v3 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-07-27 12:29 ` [PATCH v3 2/6] drm/i915/gt: document with_intel_gt_pm_if_awake() Mauro Carvalho Chehab
2022-07-27 14:18 ` [Intel-gfx] " Andi Shyti
2022-07-27 12:29 ` Mauro Carvalho Chehab [this message]
2022-07-27 12:29 ` [PATCH v3 4/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-07-27 12:29 ` [PATCH v3 5/6] drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab
2022-07-27 14:25 ` Andi Shyti
2022-07-27 12:29 ` [PATCH v3 6/6] drm/i915/gt: describe the new tlb parameter at i915_vma_resource Mauro Carvalho Chehab
2022-07-27 14:20 ` [Intel-gfx] " Andi Shyti
2022-07-28 12:08 ` [Intel-gfx] [PATCH v3 0/6] drm/i915: reduce TLB performance regressions Andi Shyti
2022-07-28 12:34 ` Mauro Carvalho Chehab
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