From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Boyd Subject: Re: [v2] msm: disp: dpu1: add support to access hw irqs regs depending on revision Date: Thu, 14 Nov 2019 09:29:40 -0800 Message-ID: <5dcd8f05.1c69fb81.bdd4.2b0a@mx.google.com> References: <1573710976-27551-1-git-send-email-dhar@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <1573710976-27551-1-git-send-email-dhar@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org To: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Cc: Shubhashree Dhar , linux-kernel@vger.kernel.org, robdclark@gmail.com, seanpaul@chromium.org, hoegsberg@chromium.org, abhinavk@codeaurora.org, jsanka@codeaurora.org, chandanu@codeaurora.org, nganji@codeaurora.org List-Id: dri-devel@lists.freedesktop.org Quoting Shubhashree Dhar (2019-11-13 21:56:16) > Current code assumes that all the irqs registers offsets can be > accessed in all the hw revisions; this is not the case for some > targets that should not access some of the irq registers. What happens if we read the irq registers that we "should not access"? Does the system reset? It would be easier to make those registers return 0 when read indicating no interrupt and ignore writes so that everything keeps working without having to skip registers. > This change adds the support to selectively remove the irqs that > are not supported in some of the hw revisions. >=20 > Change-Id: I6052b8237b703a1a9edd53893e04f7bd72223da1 Please remove these before sending upstream. > Signed-off-by: Shubhashree Dhar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +++ > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 22 +++++++++++++++++= ----- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 1 + > 4 files changed, 22 insertions(+), 5 deletions(-) >=20 > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_hw_catalog.h > index ec76b868..def8a3f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -646,6 +646,7 @@ struct dpu_perf_cfg { > * @dma_formats Supported formats for dma pipe > * @cursor_formats Supported formats for cursor pipe > * @vig_formats Supported formats for vig pipe > + * @mdss_irqs Bitmap with the irqs supported by the target Hmm pretty sure there needs to be a colon so that kernel-doc can match this but maybe I'm wrong. > */ > struct dpu_mdss_cfg { > u32 hwversion; From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1FD4C432C3 for ; Fri, 15 Nov 2019 08:05:32 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D32C52072D for ; Fri, 15 Nov 2019 08:05:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D32C52072D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD5256E0DC; Fri, 15 Nov 2019 08:05:27 +0000 (UTC) Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D21E6EE42 for ; Thu, 14 Nov 2019 17:29:42 +0000 (UTC) Received: by mail-pg1-x541.google.com with SMTP id k13so4204364pgh.3 for ; Thu, 14 Nov 2019 09:29:42 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:mime-version :content-transfer-encoding:in-reply-to:references:cc:from:subject:to :user-agent:date; bh=CcYQV1LmmMin4KfNUQWfqXUn7x+pyW1iTl5f3vQ+Lhw=; b=HIpJJkzJ3x9hOIHRqgglUXR79MOgG6z3qC3e2T95uIe07rKSpS5KOcRUUDnimwXGlr csSYjtVRo/wMnvGCyTsw8rUEgBPRyxbRpksryMMHjH7lfp6CX1PAZmDeqNPetzPN3QE2 hY43GPIPCf95Wp+CqdoxUVAZHNTdmRghQ8jX4v0nm3eEOZahjSFBogtyJ1v8BTTyg9aD 7fRCiktLyFssnuv51Dylj0MYPucySz45nuI1ol06EPh0iTJNQYyv4uKqxWskzhEkQypu QxgYzfRzBpJkfjPY41WcuvXckSNf1IdxRZAq2DSkwQM5PGhY5fPK6S3/S2yMfyr0Z7PK yBkQ== X-Gm-Message-State: APjAAAVkOjTLRkgMGrMOWxax5G7LhnFSDltj3WrXpEH7LcSW2xPFsG+V r0b3saVbDf02R0Tigka2yq1anQ== X-Google-Smtp-Source: APXvYqzty8fGyHYZm9ySVIF8pi9T97dNqEd99tGhmW7ag+BB8smmNExV5fwEnlcaxmxVHJRlf+vtew== X-Received: by 2002:aa7:8256:: with SMTP id e22mr12167282pfn.247.1573752582247; Thu, 14 Nov 2019 09:29:42 -0800 (PST) Received: from chromium.org ([2620:15c:202:1:fa53:7765:582b:82b9]) by smtp.gmail.com with ESMTPSA id i71sm6900213pfe.103.2019.11.14.09.29.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2019 09:29:41 -0800 (PST) Message-ID: <5dcd8f05.1c69fb81.bdd4.2b0a@mx.google.com> MIME-Version: 1.0 In-Reply-To: <1573710976-27551-1-git-send-email-dhar@codeaurora.org> References: <1573710976-27551-1-git-send-email-dhar@codeaurora.org> From: Stephen Boyd Subject: Re: [v2] msm: disp: dpu1: add support to access hw irqs regs depending on revision To: Shubhashree Dhar , devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org User-Agent: alot/0.8.1 Date: Thu, 14 Nov 2019 09:29:40 -0800 X-Mailman-Approved-At: Fri, 15 Nov 2019 08:05:26 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=message-id:mime-version:content-transfer-encoding:in-reply-to :references:cc:from:subject:to:user-agent:date; bh=CcYQV1LmmMin4KfNUQWfqXUn7x+pyW1iTl5f3vQ+Lhw=; b=NxMGYSTtBK4i5RPqbguGXItXdVNjv2nYm1/iGpCOqRIVhhVH6vf7946u7XMPm25GJA q7nWJkt3+Xf/XDjNbHKHgXjXTbJHCI69Wm000ian3oAhz2GlGBNz1DTe9WXQgjh7aurH DMoXuOTRdgV6nuAZHMYwbqnm9praYO+bqeVas= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Shubhashree Dhar , linux-kernel@vger.kernel.org, abhinavk@codeaurora.org, seanpaul@chromium.org, hoegsberg@chromium.org, chandanu@codeaurora.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Message-ID: <20191114172940.xshub4S9oQYmCRP5p4rDIN6O3wNByPH7LxyrWJ6Pr5Y@z> UXVvdGluZyBTaHViaGFzaHJlZSBEaGFyICgyMDE5LTExLTEzIDIxOjU2OjE2KQo+IEN1cnJlbnQg Y29kZSBhc3N1bWVzIHRoYXQgYWxsIHRoZSBpcnFzIHJlZ2lzdGVycyBvZmZzZXRzIGNhbiBiZQo+ IGFjY2Vzc2VkIGluIGFsbCB0aGUgaHcgcmV2aXNpb25zOyB0aGlzIGlzIG5vdCB0aGUgY2FzZSBm b3Igc29tZQo+IHRhcmdldHMgdGhhdCBzaG91bGQgbm90IGFjY2VzcyBzb21lIG9mIHRoZSBpcnEg cmVnaXN0ZXJzLgoKV2hhdCBoYXBwZW5zIGlmIHdlIHJlYWQgdGhlIGlycSByZWdpc3RlcnMgdGhh dCB3ZSAic2hvdWxkIG5vdCBhY2Nlc3MiPwpEb2VzIHRoZSBzeXN0ZW0gcmVzZXQ/IEl0IHdvdWxk IGJlIGVhc2llciB0byBtYWtlIHRob3NlIHJlZ2lzdGVycyByZXR1cm4KMCB3aGVuIHJlYWQgaW5k aWNhdGluZyBubyBpbnRlcnJ1cHQgYW5kIGlnbm9yZSB3cml0ZXMgc28gdGhhdCBldmVyeXRoaW5n CmtlZXBzIHdvcmtpbmcgd2l0aG91dCBoYXZpbmcgdG8gc2tpcCByZWdpc3RlcnMuCgo+IFRoaXMg Y2hhbmdlIGFkZHMgdGhlIHN1cHBvcnQgdG8gc2VsZWN0aXZlbHkgcmVtb3ZlIHRoZSBpcnFzIHRo YXQKPiBhcmUgbm90IHN1cHBvcnRlZCBpbiBzb21lIG9mIHRoZSBodyByZXZpc2lvbnMuCj4gCj4g Q2hhbmdlLUlkOiBJNjA1MmI4MjM3YjcwM2ExYTllZGQ1Mzg5M2UwNGY3YmQ3MjIyM2RhMQoKUGxl YXNlIHJlbW92ZSB0aGVzZSBiZWZvcmUgc2VuZGluZyB1cHN0cmVhbS4KCj4gU2lnbmVkLW9mZi1i eTogU2h1Ymhhc2hyZWUgRGhhciA8ZGhhckBjb2RlYXVyb3JhLm9yZz4KPiAtLS0KPiAgZHJpdmVy cy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2h3X2NhdGFsb2cuYyAgICB8ICAxICsKPiAgZHJp dmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2h3X2NhdGFsb2cuaCAgICB8ICAzICsrKwo+ ICBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfaHdfaW50ZXJydXB0cy5jIHwgMjIg KysrKysrKysrKysrKysrKystLS0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9k cHVfaHdfaW50ZXJydXB0cy5oIHwgIDEgKwo+ICA0IGZpbGVzIGNoYW5nZWQsIDIyIGluc2VydGlv bnMoKyksIDUgZGVsZXRpb25zKC0pCj4gCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9t c20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9nLmggYi9kcml2ZXJzL2dwdS9kcm0vbXNtL2Rpc3Av ZHB1MS9kcHVfaHdfY2F0YWxvZy5oCj4gaW5kZXggZWM3NmI4NjguLmRlZjhhM2YgMTAwNjQ0Cj4g LS0tIGEvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1X2h3X2NhdGFsb2cuaAo+ICsr KyBiL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9od19jYXRhbG9nLmgKPiBAQCAt NjQ2LDYgKzY0Niw3IEBAIHN0cnVjdCBkcHVfcGVyZl9jZmcgewo+ICAgKiBAZG1hX2Zvcm1hdHMg ICAgICAgIFN1cHBvcnRlZCBmb3JtYXRzIGZvciBkbWEgcGlwZQo+ICAgKiBAY3Vyc29yX2Zvcm1h dHMgICAgIFN1cHBvcnRlZCBmb3JtYXRzIGZvciBjdXJzb3IgcGlwZQo+ICAgKiBAdmlnX2Zvcm1h dHMgICAgICAgIFN1cHBvcnRlZCBmb3JtYXRzIGZvciB2aWcgcGlwZQo+ICsgKiBAbWRzc19pcnFz ICAgICAgICAgIEJpdG1hcCB3aXRoIHRoZSBpcnFzIHN1cHBvcnRlZCBieSB0aGUgdGFyZ2V0CgpI bW0gcHJldHR5IHN1cmUgdGhlcmUgbmVlZHMgdG8gYmUgYSBjb2xvbiBzbyB0aGF0IGtlcm5lbC1k b2MgY2FuIG1hdGNoCnRoaXMgYnV0IG1heWJlIEknbSB3cm9uZy4KCj4gICAqLwo+ICBzdHJ1Y3Qg ZHB1X21kc3NfY2ZnIHsKPiAgICAgICAgIHUzMiBod3ZlcnNpb247Cl9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJp LWRldmVsQGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9y Zy9tYWlsbWFuL2xpc3RpbmZvL2RyaS1kZXZlbA==