From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Jessica Zhang <quic_jesszhan@quicinc.com>,
Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>,
Marijn Suijten <marijn.suijten@somainline.org>
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>,
linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v6 6/6] drm/msm/dsi: Document DSC related pclk_rate and hdisplay calculations
Date: Sat, 10 Jun 2023 02:30:03 +0300 [thread overview]
Message-ID: <5de320ad-4b95-38ee-7a71-ba76de1a7cf5@linaro.org> (raw)
In-Reply-To: <20230405-add-dsc-support-v6-6-95eab864d1b6@quicinc.com>
On 10/06/2023 01:57, Jessica Zhang wrote:
> Add documentation comments explaining the pclk_rate and hdisplay math
> related to DSC.
>
> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index fb1d3a25765f..aeaadc18bc7b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -564,6 +564,13 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
> static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
> const struct drm_dsc_config *dsc)
> {
> + /*
> + * Adjust the pclk rate by calculating a new hdisplay proportional to
> + * the compression ratio such that:
> + * new_hdisplay = old_hdisplay * target_bpp / source_bpp
I'd say `* compressed_bpp / uncompressed_bpp'. This is easier to follow
than source and target.
> + *
> + * Porches need not be adjusted during compression.
> + */
> int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
> dsc->bits_per_component * 3);
>
> @@ -961,6 +968,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
>
> /* Divide the display by 3 but keep back/font porch and
> * pulse width same
> + *
> + * hdisplay will be divided by 3 here to account for the fact
> + * that DPU sends 3 bytes per pclk cycle to DSI.
> */
> h_total -= hdisplay;
> hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2023-06-09 23:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-09 22:57 [PATCH v6 0/6] Add DSC v1.2 Support for DSI Jessica Zhang
2023-06-09 22:57 ` [PATCH v6 1/6] msm/drm/dsi: Round up DSC hdisplay calculation Jessica Zhang
2023-06-09 22:57 ` [PATCH v6 2/6] drm/msm/dsi: Reduce pclk rate for compression Jessica Zhang
2023-06-09 23:09 ` Abhinav Kumar
2023-06-09 22:57 ` [PATCH v6 3/6] drm/msm/dpu: Add DPU_INTF_DATA_COMPRESS feature flag for DPU >= 7.0 Jessica Zhang
2023-06-09 22:57 ` [PATCH v6 4/6] drm/msm/dpu: Set DATA_COMPRESS on command mode for DCE/DSC 1.2 Jessica Zhang
2023-06-09 23:08 ` Abhinav Kumar
2023-06-13 19:04 ` Marijn Suijten
2023-06-09 22:57 ` [PATCH v6 5/6] drm/msm/dsi: Remove incorrect references to slice_count Jessica Zhang
2023-06-09 22:57 ` [PATCH v6 6/6] drm/msm/dsi: Document DSC related pclk_rate and hdisplay calculations Jessica Zhang
2023-06-09 23:30 ` Dmitry Baryshkov [this message]
2023-06-11 22:03 ` Marijn Suijten
2023-06-12 17:26 ` [Freedreno] " Abhinav Kumar
2023-06-12 18:04 ` Marijn Suijten
2023-06-15 11:31 ` [PATCH v6 0/6] Add DSC v1.2 Support for DSI Dmitry Baryshkov
2023-06-15 12:25 ` Marijn Suijten
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