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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?PY4OxDbnXz9cf65N0jqle6g/iZzEeN/9PBiyho2JpeQ5er/EG1AyTHL3G0M3?= =?us-ascii?Q?BkR4Tyo7Gz3PYZsEZlbXfV8Y+jfCwKD2ZnZYGXAgEPfEPgQWfvBVi9+XKI+w?= =?us-ascii?Q?8Z7XbFuUKYgscWmQf7PrO/1Im5txOMN21OmMy50gRc+fgO6zTrDUXNiBbjLf?= =?us-ascii?Q?GC6v44/nH49fh8dxfbqfzWvvZB6x707N0WtBEkMZXsMqkIzXAo6S6nAZLCKo?= =?us-ascii?Q?XcNH//DST/+HrfWIus989z6t3oefPC0Me8KGn6WKFUoRtVitdMMTO5KPrYjq?= =?us-ascii?Q?KItHZcygzPyxqXx5X9YE3zDDCDkA+Ih/AIPitMdZQWuA+L8jUaODRb1Oenoq?= =?us-ascii?Q?YIcAeTzZWNje2ezg15XFz0BhiugHbpDg6PF04PdW9RyI8FCFBnUOrBHeWcnS?= =?us-ascii?Q?kEI3WE2BrAWEMMI8098VzYQbiV7DNlMKhYIla25kd6Dr+b9GnMholdoabXkf?= =?us-ascii?Q?luvolmYmIkS00PN3enPwbPoEQAra5oGysnIlL1rXFmrYzI5iErVDfIs6oQje?= =?us-ascii?Q?NcoCt7yGXu/YhnzxsmWML8h5Eh/VOt3eTzYHv5kAKVhNhLSvpGZFsPLrC3Vf?= =?us-ascii?Q?nQ5LFAh5QHMQx6KtRZn1HMJeTmMJ9jgt6jUoKjP7A9oHRzxESTtCGCA6G1TC?= =?us-ascii?Q?jcjQsXqzbIi8c3SmJsMJwVzJWOzdEbxCtZKA/MVWhKTHI0hJKpWuSQ99MRWG?= =?us-ascii?Q?4qbTJyMDG3oqku1IFULHXoV3FRlQRKER4tLmb0kEtqd/oK72QDJjCTuVgj1/?= =?us-ascii?Q?tZFSCirZatcEeY32d0c6tErzDyMkRxJERjubo+PQL+GC24gluvrIQuR+AWVz?= =?us-ascii?Q?7/ETMdgYVMWF1Y1OCC+L1yUyPqO94umQHL21iFo3caSib+fSSiASudBdPnD8?= =?us-ascii?Q?Fp4JLhJXn7UjRk7NkWYia4kQoPiuduJTbOHjAwkKVT2QeSMmTll3WZI08Gwo?= =?us-ascii?Q?NSTNTA3H85B4HWe6tZ1dW2+7IaufxyYrxsomwDnjsBG9MUrwCPf0VVlp9mPP?= =?us-ascii?Q?05VFzaFBynaMHlFpKDPvl4Vhq8ykOn+r7/YqcrjhlLHrTZ6kHCFF+MCjQ6D0?= =?us-ascii?Q?2Ou6bGeCWHm/pHZVJ25d4p7XOQnHgxoTBS80P5PJPlo4eDnwnCHzJCfbb/gM?= =?us-ascii?Q?3CrnggEi0BGq1obD+7HHPitqzov3cENf7sLPpRzmPW9QLceZpJdJ35XUIAVj?= =?us-ascii?Q?/XktKj7oKFiU4goj39BSXJfc2JevvUfoABYFjGkHP4YIrJYIQna0lpRNlzmr?= =?us-ascii?Q?hqc4m4jj+0dLv5C1FcakfCHdbWXuWp/wIxR1uNZswKe5E0K49hepTE+oLguA?= =?us-ascii?Q?R0zdrYpXV0NchDn/B/ivbIISKXmQejr7Omyw2YfN4LsSa8lzEoV209WfZ/OR?= =?us-ascii?Q?d/KlDwXwTJ8/Ah7CY/t7R36yWM63EX+wjPFNyxJX5b3tdyKtRW0REMhF0m2R?= =?us-ascii?Q?vttEW4KcFgUg3MaFxv4eSsIBIbOfbNZPiR1C4QWBAVaJwre4Ziz7MaV9e+R3?= =?us-ascii?Q?EOdhEsgw5PmBx/5zS5M0KiMBl9OPQomIgdp/mYUnc0/3Wik5Uvv+n30/mVib?= =?us-ascii?Q?GFTNIOzQIruZIxGuiFI92R502Tl4u35XkUYoKASotfPJgKbSan4olZsx/zvj?= =?us-ascii?Q?4g=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 400a301f-eb12-429c-c2d9-08db53060d60 X-MS-Exchange-CrossTenant-AuthSource: CY5PR11MB6139.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 May 2023 16:29:26.5306 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 6c38i+HvNUW/mdconMRBbgwT/BWZAjDuirGwmll5lw7HnVCDGTp0KFzpBNMSoMTEByS0Skgl2dONzaP/5l57rLQ7isTAcH6Ih1ceF2d+PPM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4738 X-OriginatorOrg: intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Morton , Christian =?utf-8?B?S8O2bmln?= , intel-gfx@lists.freedesktop.org, Kevin Brodsky , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Alex Deucher , Thomas Gleixner , Masahiro Yamada Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, May 12, 2023 at 02:14:19PM +0300, Andy Shevchenko wrote: >On Mon, May 08, 2023 at 10:14:02PM -0700, Lucas De Marchi wrote: >> Add GENMASK_U32(), GENMASK_U16() and GENMASK_U8() macros to create >> masks for fixed-width types and also the corresponding BIT_U32(), >> BIT_U16() and BIT_U8(). > >Why? to create the masks/values for device registers that are of a certain width, preventing mistakes like: #define REG1 0x10 #define REG1_ENABLE BIT(17) #define REG1_FOO GENMASK(16, 15); register_write(REG1_ENABLE, REG1); ... if REG1 is a 16bit register for example. There were mistakes in the past in the i915 source leading to the creation of the REG_* variants on top of normal GENMASK/BIT (see last patch and commit 09b434d4f6d2 ("drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contents") We are preparing another driver (xe), still to be merged but already open (https://gitlab.freedesktop.org/drm/xe/kernel), that has similar requirements. > >> All of those depend on a new "U" suffix added to the integer constant. >> Due to naming clashes it's better to call the macro U32. Since C doesn't >> have a proper suffix for short and char types, the U16 and U18 variants >> just use U32 with one additional check in the BIT_* macros to make >> sure the compiler gives an error when the those types overflow. >> The BIT_U16() and BIT_U8() need the help of GENMASK_INPUT_CHECK(), >> as otherwise they would allow an invalid bit to be passed. Hence >> implement them in include/linux/bits.h rather than together with >> the other BIT* variants. > >So, we have _Generic() in case you still wish to implement this. humn... how would a _Generic() help here? The input is 1 or 2 integer literals (h and l) so the compiler can check it is correct at build time. See example above. Lucas De Marchi