From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA457C433ED for ; Sat, 1 May 2021 04:01:50 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 28473613C2 for ; Sat, 1 May 2021 04:01:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 28473613C2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CB84F6F883; Sat, 1 May 2021 04:01:46 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id E05836F612; Sat, 1 May 2021 04:01:44 +0000 (UTC) IronPort-SDR: nkENm5XeP5xwZ2RrSJYRB/nSkpV5h3ESRiL04pgEJql2fy9vRrb0M/rae40F0qChNYoKzjgfSx Am5/tW5Se9fw== X-IronPort-AV: E=McAfee;i="6200,9189,9970"; a="218162828" X-IronPort-AV: E=Sophos;i="5.82,264,1613462400"; d="scan'208";a="218162828" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 21:01:43 -0700 IronPort-SDR: UmFn0t/vT630guBFMIYrA9U2D7udxfjM+CwD6fPCdaSUY4wQRQrNQguyxdnch+bWWOtOnlCqb4 OVz/AEprmP2w== X-IronPort-AV: E=Sophos;i="5.82,264,1613462400"; d="scan'208";a="459856998" Received: from adixit-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.201.129]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Apr 2021 21:01:43 -0700 Date: Fri, 30 Apr 2021 21:01:42 -0700 Message-ID: <878s4zayqh.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa Subject: Re: [PATCH 1/1] i915/query: Correlate engine and cpu timestamps with better accuracy In-Reply-To: <20210501021959.GA50683@orsosgc001.ra.intel.com> References: <20210429003410.69754-1-umesh.nerlige.ramappa@intel.com> <20210429003410.69754-2-umesh.nerlige.ramappa@intel.com> <20210430222609.GC38093@orsosgc001.ra.intel.com> <87czubbco1.wl-ashutosh.dixit@intel.com> <179255a3b48.2817.c6988b7ea6112e3e892765a0d4287e0c@jlekstrand.net> <20210501021959.GA50683@orsosgc001.ra.intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel GFX , Maling list - DRI developers , Jason Ekstrand Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, 30 Apr 2021 19:19:59 -0700, Umesh Nerlige Ramappa wrote: > > On Fri, Apr 30, 2021 at 07:35:41PM -0500, Jason Ekstrand wrote: > > On April 30, 2021 18:00:58 "Dixit, Ashutosh" > > wrote: > > > > On Fri, 30 Apr 2021 15:26:09 -0700, Umesh Nerlige Ramappa wrote: > > > > Looks like the engine can be dropped since all timestamps are in = sync. > > I > > just have one more question here. The timestamp itself is 36 bits. > > =A0Should > > the uapi also report the timestamp width to the user OR should I = just > > return the lower 32 bits of the timestamp? > > > > Yeah, I think reporting the timestamp width is a good idea since we're > > reporting the period/frequency here. > > Actually, I forgot that we are handling the overflow before returning the > cs_cycles to the user and overflow handling was the only reason I thought > user should know the width. Would you stil recommend returning the width = in > the uapi? The width is needed for userspace to figure out if overflow has occured between two successive query calls. I don't think I see this happening in the code. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel