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([2001:16b8:e981:9e00:815a:6661:46b9:139d]) by smtp.gmail.com with ESMTPSA id dn4-20020a17090794c400b006dbec4f4acbsm10869995ejc.6.2022.04.10.04.31.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 10 Apr 2022 04:31:25 -0700 (PDT) Message-ID: <8fac5d72-c635-521c-e7d1-a3980a4ed719@gmail.com> Date: Sun, 10 Apr 2022 13:31:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v10 12/24] drm/rockchip: dw_hdmi: drop mode_valid hook Content-Language: en-US To: Sascha Hauer , dri-devel@lists.freedesktop.org References: <20220408112238.1274817-1-s.hauer@pengutronix.de> <20220408112238.1274817-13-s.hauer@pengutronix.de> From: Alex Bee In-Reply-To: <20220408112238.1274817-13-s.hauer@pengutronix.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Benjamin Gaignard , Peter Geis , Sandy Huang , linux-rockchip@lists.infradead.org, Michael Riesch , kernel@pengutronix.de, Andy Yan , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Am 08.04.22 um 13:22 schrieb Sascha Hauer: > The driver checks if the pixel clock of the given mode matches an entry > in the mpll config table. The frequencies in the mpll table are meant as > a frequency range up to which the entry works, not as a frequency that > must match the pixel clock. The downstream Kernel also does not have > this check, so drop it to allow for more display resolutions. > > Signed-off-by: Sascha Hauer > --- > You're correct: That frequency is meant to be greater or equal. But I'm not sure if it makes sense to completely drop it - what happens for clocks rates > 600 MHz which might be supported by later generation sinks (HDMI 2.1 or later)? As these are not supported by the IPs/PHYs currently supported by that driver a reason a simple int i; for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { - if (pclk == mpll_cfg[i].mpixelclock) { + if (pclk >= mpll_cfg[i].mpixelclock) { valid = true; break; } would be the better idea, I guess. Regards, Alex > Notes: > Changes since v3: > - new patch > > drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 --------------------- > 1 file changed, 25 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > index cb43e7b47157d..008ab20f39ee6 100644 > --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c > @@ -248,26 +248,6 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi) > return 0; > } > > -static enum drm_mode_status > -dw_hdmi_rockchip_mode_valid(struct dw_hdmi *hdmi, void *data, > - const struct drm_display_info *info, > - const struct drm_display_mode *mode) > -{ > - const struct dw_hdmi_mpll_config *mpll_cfg = rockchip_mpll_cfg; > - int pclk = mode->clock * 1000; > - bool valid = false; > - int i; > - > - for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) { > - if (pclk == mpll_cfg[i].mpixelclock) { > - valid = true; > - break; > - } > - } > - > - return (valid) ? MODE_OK : MODE_BAD; > -} > - > static void dw_hdmi_rockchip_encoder_disable(struct drm_encoder *encoder) > { > } > @@ -433,7 +413,6 @@ static struct rockchip_hdmi_chip_data rk3228_chip_data = { > }; > > static const struct dw_hdmi_plat_data rk3228_hdmi_drv_data = { > - .mode_valid = dw_hdmi_rockchip_mode_valid, > .mpll_cfg = rockchip_mpll_cfg, > .cur_ctr = rockchip_cur_ctr, > .phy_config = rockchip_phy_config, > @@ -450,7 +429,6 @@ static struct rockchip_hdmi_chip_data rk3288_chip_data = { > }; > > static const struct dw_hdmi_plat_data rk3288_hdmi_drv_data = { > - .mode_valid = dw_hdmi_rockchip_mode_valid, > .mpll_cfg = rockchip_mpll_cfg, > .cur_ctr = rockchip_cur_ctr, > .phy_config = rockchip_phy_config, > @@ -470,7 +448,6 @@ static struct rockchip_hdmi_chip_data rk3328_chip_data = { > }; > > static const struct dw_hdmi_plat_data rk3328_hdmi_drv_data = { > - .mode_valid = dw_hdmi_rockchip_mode_valid, > .mpll_cfg = rockchip_mpll_cfg, > .cur_ctr = rockchip_cur_ctr, > .phy_config = rockchip_phy_config, > @@ -488,7 +465,6 @@ static struct rockchip_hdmi_chip_data rk3399_chip_data = { > }; > > static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = { > - .mode_valid = dw_hdmi_rockchip_mode_valid, > .mpll_cfg = rockchip_mpll_cfg, > .cur_ctr = rockchip_cur_ctr, > .phy_config = rockchip_phy_config, > @@ -501,7 +477,6 @@ static struct rockchip_hdmi_chip_data rk3568_chip_data = { > }; > > static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = { > - .mode_valid = dw_hdmi_rockchip_mode_valid, > .mpll_cfg = rockchip_mpll_cfg, > .cur_ctr = rockchip_cur_ctr, > .phy_config = rockchip_phy_config,