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From: Alexandre Mergnat <amergnat@baylibre.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: dri-devel@lists.freedesktop.org,
	"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
	"Matthias Brugger" <matthias.bgg@gmail.com>,
	linux-mediatek@lists.infradead.org,
	"Will Deacon" <will@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	"CK Hu" <ck.hu@mediatek.com>, "Rob Herring" <robh+dt@kernel.org>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"David Airlie" <airlied@gmail.com>,
	"Xinlei Lee" <xinlei.lee@mediatek.com>,
	"Jitao Shi" <jitao.shi@mediatek.com>,
	linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Fabien Parent" <fparent@baylibre.com>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Chun-Kuang Hu" <chunkuang.hu@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>
Subject: Re: [PATCH 14/18] drm/mediatek: dpi: add support for dpi clock
Date: Tue, 16 Apr 2024 16:53:06 +0200	[thread overview]
Message-ID: <96d90ddd-2910-4419-ba90-64a09a3dbf1e@baylibre.com> (raw)
In-Reply-To: <cf25a3cc-6411-45f5-bc7a-6b69cf28c860@collabora.com>



On 24/10/2023 11:12, AngeloGioacchino Del Regno wrote:
> Il 23/10/23 16:40, amergnat@baylibre.com ha scritto:
>> From: Fabien Parent <fparent@baylibre.com>
>>
>> MT8365 requires an additional clock for DPI. Add support for that
>> additional clock.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> 
> I'm not convinced that this is right... at all.
> 
>  From a fast check of the MT8365 DPI clocks, I can see that the DPI0 
> clock declares
> parent VPLL_DPIX (a fixed clock), but nothing ever has VPLL_DPIX_EN 
> (which is the
> GATE clock, enabling output of DPIx VPLL?).
> 
> But then, there's even more: no clock ever references the 
> CLK_TOP_DPI0_SEL nor the
> CLK_TOP_DPI1_SEL gate, which is a PLL parent selector... in other 
> platforms, that
> is muxing through the TVDPLL, but on MT8365 that is LVDSPLL?!

AFAI see into mt8365 documentation, there is no TVDPLL, only LVDSPLL

> 
> I have many questions now:
> * Two PLLs are apparently brought up, but which one is the right one?!
>    * Is the LVDS PLL really used for DisplayPort? (dpi0_sel)

Seems to be LVDS

                                  enable  prepare  protect                                duty  hardware
    clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
  clk26m                              18       19        1    26000000          0     0         Y
     vpll_dpix                         1        1        0    75000000          0     0  50000         Y
        mm_flvdstx_pxl                 0        0        0    75000000          0     0  50000         N
        mm_dpi0_dpi0                   1        1        0    75000000          0     0  50000         Y
        vpll_dpix_en                   0        0        0    75000000          0     0  50000         N
     lvdspll                           1        1        0   283999497          0     0  50000         Y
        lvdspll_d16                    0        0        0    17749968          0     0  50000         Y
        lvdspll_d8                     0        0        0    35499937          0     0  50000         Y
        lvdspll_d4                     0        0        0    70999874          0     0  50000         Y
        lvdspll_d2                     1        1        0   141999748          0     0  50000         Y
           dpi0_sel                    1        1        0   141999748          0     0  50000         Y
           dpi1_sel                    0        0        0   141999748          0     0  50000         N
     mmpll                             1        1        0   456999909          0     0  50000         Y
        mmpll_ck                       1        1        0   456999909          0     0  50000         Y
           mm_sel                     15       15        0   456999909          0     0  50000         Y
              mm_dpi0                  1        1        0   456999909          0     0  50000         Y



> * Are you sure that CLK_MM_DPI0_DPI0's parent shouldn't be dpi0_sel 
> instead?

I'm agree with you. After few change, it works.

-       GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "vpll_dpix", 20),
+       GATE_MM0(CLK_MM_DPI0_DPI0, "mm_dpi0_dpi0", "dpi0_sel", 20),

-                       clocks = <&topckgen CLK_TOP_DPI0_SEL>,
+                       clocks = <&mmsys CLK_MM_DPI0_DPI0>,


                                  enable  prepare  protect                                duty  hardware
    clock                          count    count    count        rate   accuracy phase  cycle    enable
-------------------------------------------------------------------------------------------------------
     vpll_dpix                        0       0        0        75000000    0          0     50000      Y
        mm_flvdstx_pxl                0       0        0        75000000    0          0     50000      N
        vpll_dpix_en                  0       0        0        75000000    0          0     50000      N

     lvdspll                          1       1        0        283999497   0          0     50000      Y
        lvdspll_d16                   0       0        0        17749968    0          0     50000      Y
        lvdspll_d8                    0       0        0        35499937    0          0     50000      Y
        lvdspll_d4                    0       0        0        70999874    0          0     50000      Y
        lvdspll_d2                    1       1        0        141999748   0          0     50000      Y
           dpi0_sel                   1       1        0        141999748   0          0     50000      Y
              mm_dpi0_dpi0            1       1        0        141999748   0          0     50000      Y
           dpi1_sel                   0       0        0        141999748   0          0     50000      N

     mmpll                            1       1        0        456999909   0          0     50000      Y
        mmpll_d2                      0       0        0        228499954   0          0     50000      Y
        mmpll_ck                      1       1        0        456999909   0          0     50000      Y
           mm_sel                     15      15       0        456999909   0          0     50000      Y
              mm_dpi0                 1       1        0        456999909   0          0     50000      Y


> * Where is DPI1 in this SoC? Why is there a dpi1_sel clock, but no MM clock
>    for the DPI1 controller? Is there any DPI1 controller, even?!

DPI1 isn't documented.

>    * Why is there a DPI1 MUX, if there's no DPI1 controller?!

Good question, I don't know. Legacy of the downstream code.

That will be fixed for the next version.

-- 
Regards,
Alexandre

  reply	other threads:[~2024-04-16 14:53 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23 14:40 [PATCH 00/18] Add display support for the MT8365-EVK board Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 01/18] dt-bindings: display: mediatek: aal: add binding for MT8365 SoC Alexandre Mergnat
2023-10-23 17:03   ` Conor Dooley
2023-10-23 14:40 ` [PATCH 02/18] dt-bindings: display: mediatek: ccorr: " Alexandre Mergnat
2023-10-23 17:31   ` Conor Dooley
2023-10-23 17:33     ` Conor Dooley
2023-10-23 14:40 ` [PATCH 03/18] dt-bindings: display: mediatek: color: " Alexandre Mergnat
2023-10-24  9:40   ` Chen-Yu Tsai
2023-10-24  9:47     ` Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 04/18] dt-bindings: display: mediatek: dither: " Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 05/18] dt-bindings: display: mediatek: dsi: " Alexandre Mergnat
2023-10-24 20:30   ` Rob Herring
2023-10-25  7:35     ` Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 06/18] dt-bindings: display: mediatek: dpi: add power-domains property amergnat
2023-10-23 14:40 ` [PATCH 07/18] dt-bindings: display: mediatek: dpi: add binding for MT8365 amergnat
2023-10-23 14:40 ` [PATCH 08/18] dt-bindings: display: mediatek: gamma: add binding for MT8365 SoC Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 09/18] dt-bindings: display: mediatek: ovl: " Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 10/18] dt-bindings: display: mediatek: rdma: " Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 11/18] dt-bindings: pwm: add power-domains property Alexandre Mergnat
2023-10-23 17:38   ` Conor Dooley
2023-10-24  9:21     ` Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 12/18] dt-bindings: pwm: add binding for mt8365 SoC Alexandre Mergnat
2023-10-23 17:35   ` Conor Dooley
2023-10-23 21:44   ` Uwe Kleine-König
2023-12-06 17:38     ` Uwe Kleine-König
2023-10-24  9:16   ` AngeloGioacchino Del Regno
2023-10-23 14:40 ` [PATCH 13/18] drm/mediatek: dsi: Improves the DSI lane setup robustness Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 14/18] drm/mediatek: dpi: add support for dpi clock amergnat
2023-10-24  9:12   ` AngeloGioacchino Del Regno
2024-04-16 14:53     ` Alexandre Mergnat [this message]
2023-10-23 14:40 ` [PATCH 15/18] drm/mediatek: add MT8365 SoC support amergnat
2023-10-24  9:20   ` AngeloGioacchino Del Regno
2023-10-23 14:40 ` [PATCH 16/18] arm64: defconfig: enable display connector support Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 17/18] arm64: dts: mediatek: add display blocks support for the MT8365 SoC Alexandre Mergnat
2023-10-23 14:40 ` [PATCH 18/18] arm64: dts: mediatek: add display support for mt8365-evk Alexandre Mergnat

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