From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rajeev Nandan <quic_rajeevny@quicinc.com>
Cc: quic_kalyant@quicinc.com, freedreno@lists.freedesktop.org,
jonathan@marek.ca, devicetree@vger.kernel.org, airlied@linux.ie,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, quic_abhinavk@quicinc.com,
robh+dt@kernel.org, quic_mkrishn@quicinc.com,
swboyd@chromium.org, sean@poorly.run
Subject: Re: [v1 1/2] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties
Date: Thu, 30 Dec 2021 17:00:49 +0300 [thread overview]
Message-ID: <CAA8EJpptEvS6Y+MEX=VxmUSf1=GAp_oV5PWCCGUzMYP13_QsRg@mail.gmail.com> (raw)
In-Reply-To: <1640856276-14697-2-git-send-email-quic_rajeevny@quicinc.com>
On Thu, 30 Dec 2021 at 12:25, Rajeev Nandan <quic_rajeevny@quicinc.com> wrote:
>
> Add 10nm dsi phy tuning properties for phy drive strength and
> phy drive level adjustemnt.
>
> Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
> ---
> .../devicetree/bindings/display/msm/dsi-phy-10nm.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> index 4399715..9406982 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> @@ -35,6 +35,18 @@ properties:
> Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
> connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
>
> + phy-drive-strength-cfg:
> + type: array
> + description:
> + Register values of DSIPHY_RESCODE_OFFSET_TOP and DSIPHY_RESCODE_OFFSET_BOT
> + for all five lanes to adjust the phy drive strength.
> +
> + phy-drive-level-cfg:
> + type: array
> + description:
> + Register values of DSIPHY_RESCODE_OFFSET_TOP for all five lanes to adjust
> + phy drive level/amplitude.
Description is incorrect, it's not the RESCODE_OFFSET_TOP register.
> +
> required:
> - compatible
> - reg
> @@ -64,5 +76,12 @@ examples:
> clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "ref";
> +
> + phy-drive-strength-cfg = [00 00
> + 00 00
> + 00 00
> + 00 00
> + 00 00];
> + phy-drive-level-cfg = [59 59 59 59 59];
You are writing this value into the PHY_CMN_VREG_CTRL register. So
specifying 5 values here does not make sense.
> };
> ...
> --
> 2.7.4
>
--
With best wishes
Dmitry
next prev parent reply other threads:[~2021-12-30 14:01 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-30 9:24 [v1 0/2] drm/msm/dsi: Add 10nm dsi phy tuning configuration support Rajeev Nandan
2021-12-30 9:24 ` [v1 1/2] dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties Rajeev Nandan
2021-12-30 14:00 ` Dmitry Baryshkov [this message]
2021-12-30 14:14 ` Dmitry Baryshkov
2022-01-01 22:01 ` Rob Herring
2022-01-06 2:07 ` Stephen Boyd
2021-12-30 9:24 ` [v1 2/2] drm/msm/dsi: Add 10nm dsi phy tuning configuration support Rajeev Nandan
2021-12-30 14:39 ` Dmitry Baryshkov
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