On Tue, Jun 09, 2020 at 03:57:04AM +0800, Cyrus Lien wrote:
> According to EDID spec, table 3.26, byte #6 and #8, which said "Minimum
> rate value shall be less than or equal to maximum rate value". The minimum
> horizontal/vertical rate value is able to be equal to maximum horizontal/
> veritcal rate value.
How does that justifiy ignoring the min value?
Indeed, this patch does not make sense.
Setting minimum horizontal rate equal to maximum horizontal rate is a request come from AMD Windows graphic driver for support freesync (I'm not sure if linux AMD driver also require it).
The problem is mode_in_hsync_range always return false except the mode's hsync exactly equal to hmax and hmin.
Add print in mode_in_hsync_range():
[drm] mode_in_hsync_range 1920x1200: hsync: 94, hmax: 110, hmix:110
[drm] mode_in_hsync_range 1920x1200: hsync: 107, hmax: 110, hmix:110
[drm] mode_in_hsync_range 1920x1200: hsync: 152, hmax: 110, hmix:110
[drm] mode_in_hsync_range 1920x1440: hsync: 90, hmax: 110, hmix:110
[drm] mode_in_hsync_range 1920x1440: hsync: 113, hmax: 110, hmix:110
[drm] mode_in_hsync_range 1920x1440: hsync: 183, hmax: 110, hmix:110
Is it available to get or calculate the hmax, hmix value from other fields in EDID ?
Would you please provide some advice or directions to solve this problem ? Thank you and appreciated the help.
edid-decode (hex):
00 ff ff ff ff ff ff 00 06 af 9b 32 00 00 00 00
00 1e 01 04 b5 26 15 78 03 1f 95 a5 53 35 b5 26
0f 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 70 d0 00 a0 f0 70 3e 80 30 20
35 00 7d d6 10 00 00 1a 00 00 00 fd 00 32 5a 6e
6e 17 01 11 01 e0 60 20 50 3c 00 00 00 fe 00 34
34 54 52 4e 15 42 31 37 33 5a 41 4e 00 00 00 00
00 05 81 01 28 00 12 00 00 0b 01 0a 20 20 01 af
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
----------------
EDID version: 1.4
Manufacturer: AUO Model 12955 Serial Number 0
Made in year 2020
Digital display
10 bits per primary color channel
DisplayPort interface
Maximum image size: 38 cm x 21 cm
Gamma: 2.20
Supported color formats: RGB 4:4:4
First detailed timing includes the native pixel format and preferred refresh rate
Display is continuous frequency
Color Characteristics
Red: 0.6445, 0.3251
Green: 0.2099, 0.7099
Blue: 0.1503, 0.0595
White: 0.3134, 0.3291
Established Timings I & II: none
Standard Timings: none
Detailed mode: Clock 533.600 MHz, 381 mm x 214 mm
3840 3888 3920 4000 ( 48 32 80)
2160 2163 2168 2222 ( 3 5 54)
+hsync -vsync
VertFreq: 60.036 Hz, HorFreq: 133.400 kHz
Display Range Limits
Monitor ranges (Bare Limits): 50-90 Hz V, 110-110 kHz H, max dotclock 230 MHz
Alphanumeric Data String: 44TRN
Manufacturer-Specified Display Descriptor (0x00): 00 00 00 05 81 01 28 00 12 00 00 0b 01 0a 20 20 ......(.......
Has 1 extension block
Checksum: 0xaf
----------------
>
> This change check if h/v-sync excess maximum horizontal/vertical rate if
> hmin equal to hmax or vmin equal to vmax.
>
> Signed-off-by: Cyrus Lien <cyrus.lien@canonical.com>
> ---
> drivers/gpu/drm/drm_edid.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index fed653f13c26..23878320eabd 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c
> @@ -2674,6 +2674,9 @@ mode_in_hsync_range(const struct drm_display_mode *mode,
> hmax += ((t[4] & 0x08) ? 255 : 0);
> hsync = drm_mode_hsync(mode);
>
> + if (hmax == hmin)
> + return (hsync <= hmax);
> +
> return (hsync <= hmax && hsync >= hmin);
> }
>
> @@ -2691,6 +2694,9 @@ mode_in_vsync_range(const struct drm_display_mode *mode,
> vmax += ((t[4] & 0x02) ? 255 : 0);
> vsync = drm_mode_vrefresh(mode);
>
> + if (vmax == vmin)
> + return (vsync <= vmax);
> +
> return (vsync <= vmax && vsync >= vmin);
> }
>
> --
> 2.25.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Ville Syrjälä
Intel