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[209.85.217.47]) by smtp.gmail.com with ESMTPSA id w64sm182424vke.46.2020.06.01.17.31.05 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Jun 2020 17:31:05 -0700 (PDT) Received: by mail-vs1-f47.google.com with SMTP id k13so1013160vsm.13 for ; Mon, 01 Jun 2020 17:31:05 -0700 (PDT) X-Received: by 2002:a67:b14b:: with SMTP id z11mr15793449vsl.109.1591057865161; Mon, 01 Jun 2020 17:31:05 -0700 (PDT) MIME-Version: 1.0 References: <20200601083309.712606-1-sam@ravnborg.org> <20200601083309.712606-5-sam@ravnborg.org> In-Reply-To: <20200601083309.712606-5-sam@ravnborg.org> From: Doug Anderson Date: Mon, 1 Jun 2020 17:30:53 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 4/6] drm: panel-simple: add Hitachi 3.5" QVGA panel To: Sam Ravnborg X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Sebastian Reichel , dri-devel , Bjorn Andersson , Thierry Reding , =?UTF-8?Q?S=C3=B8ren_Andersen?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On Mon, Jun 1, 2020 at 1:33 AM Sam Ravnborg wrote: > > This panel is used on evaluation boards for Atmel at91sam9261 and > at91sam6263. > > Signed-off-by: Sam Ravnborg > Cc: Thierry Reding > Cc: Sam Ravnborg > --- > drivers/gpu/drm/panel/panel-simple.c | 29 ++++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c > index 8624bb80108c..25c96639631f 100644 > --- a/drivers/gpu/drm/panel/panel-simple.c > +++ b/drivers/gpu/drm/panel/panel-simple.c > @@ -1813,6 +1813,32 @@ static const struct panel_desc hannstar_hsd100pxn1 = { > .connector_type = DRM_MODE_CONNECTOR_LVDS, > }; > > +static const struct drm_display_mode hitachi_tx09d71vm1cca_mode = { > + .clock = 4965000, This is the pixel clock in kHz, right? So it runs at almost 5 Terahertz? > + .hdisplay = 240, > + .hsync_start = 240 + 0, > + .hsync_end = 240 + 0 + 5, > + .htotal = 240 + 0 + 5 + 1, > + .vdisplay = 320, > + .vsync_start = 320 + 0, > + .vsync_end = 320 + 0 + 1, > + .vtotal = 320 + 0 + 1 + 1, Some random datasheet I found has really different numbers. If the numbers above are what everyone is using then I suppose it's fine, just curious why the mismatch. Also: should you provide "vrefresh"? -Doug _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel