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dmarc=none (p=none dis=none) header.from=anholt.net Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D9D7F6E3A6; Wed, 27 May 2020 19:24:57 +0000 (UTC) Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FAFF6E3A6 for ; Wed, 27 May 2020 19:24:56 +0000 (UTC) Received: by mail-lj1-x243.google.com with SMTP id b6so30395254ljj.1 for ; Wed, 27 May 2020 12:24:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=anholt-net.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=B06LJB5h/zgyW4gA7PYFxNZx20JgVf522YB+3F5h4TA=; b=u+9b6a0UuzqNEdKrRRYp74xaFel684WNim59ka+OYrYbmLKL+H/nprkX7vFkVdiCUa +O86fHKLZqw/5tvWP3hqw33ak6tHjf4NSI1j5fKipCDJdZkSuCUv1XCSLH8Tfb6vMsFa +KsDYhqcUq9p3f4rUyvTwRp9v9Amptoi+GEESpmqsgMwwWNwe5Zu3KFM4nYbIyauEQQW Usd8sT8LWVX1IsdfL24D+BCSQx7pVofPBfOZl09tfusTjauehsiP52sutkoRRUjTp+ui nESEZOg8iF63hA/Zd9X5L9zSoARxejFqZOUOXEg2msmKduDEaDnFqQPCGDpRoIWyLiqu vDtA== X-Google-DKIM-Signature: v=1; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, May 27, 2020 at 8:50 AM Maxime Ripard wrote: > > The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add > support for them. > > Signed-off-by: Maxime Ripard > --- > drivers/gpu/drm/vc4/vc4_crtc.c | 84 ++++++++++++++++++++++++++++++++++- > drivers/gpu/drm/vc4/vc4_regs.h | 6 +++- > 2 files changed, 88 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index 9efd7cb25590..a577ed8f929f 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -229,6 +229,13 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) > case PV_CONTROL_FORMAT_24: > case PV_CONTROL_FORMAT_DSIV_24: > default: > + /* > + * For some reason, the pixelvalve4 doesn't work with > + * the usual formula and will only work with 32. > + */ > + if (vc4_crtc->data->hvs_output == 5) > + return 32; > + > return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; > } > } > @@ -237,9 +244,14 @@ static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, > u32 format) > { > u32 level = vc4_get_fifo_full_level(vc4_crtc, format); > + u32 ret = 0; > > - return VC4_SET_FIELD(level & 0x3f, > - PV_CONTROL_FIFO_LEVEL); > + if (level > 0x3f) > + ret |= VC4_SET_FIELD((level >> 6) & 0x3, > + PV5_CONTROL_FIFO_LEVEL_HIGH); > + I would drop the conditional here (ORing in zero is fine), and also the & 3 because it would be good to get a warning if you picked a fifo full level that doesn't fit in the field. > + return ret | VC4_SET_FIELD(level & 0x3f, > + PV_CONTROL_FIFO_LEVEL); > } > > /* > @@ -277,6 +289,8 @@ static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) > > static void vc4_crtc_config_pv(struct drm_crtc *crtc) > { > + struct drm_device *dev = crtc->dev; > + struct vc4_dev *vc4 = to_vc4_dev(dev); > struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); > struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); > struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); > @@ -356,6 +370,10 @@ static void vc4_crtc_config_pv(struct drm_crtc *crtc) > if (is_dsi) > CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); > > + if (vc4->hvs->hvs5) > + CRTC_WRITE(PV_MUX_CFG, > + VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); Can we get some #defines in the reg header instead of a magic value? Other than that, r-b. _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel