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* [PATCH] drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly
@ 2022-08-23  6:44 jinsdb
  2022-08-25 15:56 ` Alex Deucher
  0 siblings, 1 reply; 2+ messages in thread
From: jinsdb @ 2022-08-23  6:44 UTC (permalink / raw)
  To: alexander.deucher, christian.koenig, Xinhui.Pan, airlied, daniel
  Cc: jinsdb, dri-devel, amd-gfx, linux-kernel

From: Qu Huang <jinsdb@126.com>

The mmVM_L2_CNTL3 register is not assigned an initial value

Signed-off-by: Qu Huang <jinsdb@126.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 1da2ec692057e..b8a987a032a8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -176,6 +176,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 	tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 	WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);

+	tmp = mmVM_L2_CNTL3_DEFAULT;
 	if (adev->gmc.translate_further) {
 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 		tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
--
2.31.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly
  2022-08-23  6:44 [PATCH] drm/amdgpu: mmVM_L2_CNTL3 register not initialized correctly jinsdb
@ 2022-08-25 15:56 ` Alex Deucher
  0 siblings, 0 replies; 2+ messages in thread
From: Alex Deucher @ 2022-08-25 15:56 UTC (permalink / raw)
  To: jinsdb
  Cc: airlied, Xinhui.Pan, linux-kernel, dri-devel, amd-gfx,
	alexander.deucher, christian.koenig

Applied.  Thanks!

Alex

On Tue, Aug 23, 2022 at 3:15 AM <jinsdb@126.com> wrote:
>
> From: Qu Huang <jinsdb@126.com>
>
> The mmVM_L2_CNTL3 register is not assigned an initial value
>
> Signed-off-by: Qu Huang <jinsdb@126.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 1da2ec692057e..b8a987a032a8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -176,6 +176,7 @@ static void mmhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
>         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
>         WREG32_SOC15(MMHUB, 0, mmVM_L2_CNTL2, tmp);
>
> +       tmp = mmVM_L2_CNTL3_DEFAULT;
>         if (adev->gmc.translate_further) {
>                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
>                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
> --
> 2.31.1
>

^ permalink raw reply	[flat|nested] 2+ messages in thread

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2022-08-25 15:56 ` Alex Deucher

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