From: Stephen Boyd <swboyd@chromium.org>
To: Kuogee Hsieh <quic_khsieh@quicinc.com>,
agross@kernel.org, airlied@linux.ie, bjorn.andersson@linaro.org,
daniel@ffwll.ch, dmitry.baryshkov@linaro.org,
dri-devel@lists.freedesktop.org, robdclark@gmail.com,
sean@poorly.run, vkoul@kernel.org
Cc: quic_sbillaka@quicinc.com, linux-arm-msm@vger.kernel.org,
quic_abhinavk@quicinc.com, linux-kernel@vger.kernel.org,
quic_aravindh@quicinc.com, freedreno@lists.freedesktop.org
Subject: Re: [PATCH v10 3/4] drm/msm/dpu: revise timing engine programming to support widebus feature
Date: Fri, 25 Feb 2022 10:13:56 -0800 [thread overview]
Message-ID: <CAE-0n506iRCF0TjPDT2Aqe--RXEJbPe8961JiGmW6K2M5VJRUw@mail.gmail.com> (raw)
In-Reply-To: <1645576060-3046-4-git-send-email-quic_khsieh@quicinc.com>
Quoting Kuogee Hsieh (2022-02-22 16:27:39)
> Widebus feature will transmit two pixel data per pixel clock to interface.
> Timing engine provides driving force for this purpose. This patch base
> on HPG (Hardware Programming Guide) to revise timing engine register
> setting to accommodate both widebus and non widebus application. Also
> horizontal width parameters need to be reduced by half since two pixel
> data are clocked out per pixel clock when widebus feature enabled.
>
> Widebus can be enabled individually at DP. However at DSI, widebus have
> to be enabled along with DSC to achieve pixel clock rate be scaled down
> with same ratio as compression ratio when 10 bits per source component.
> Therefore this patch add no supports of DSI related widebus and compression.
>
> Changes in v2:
> -- remove compression related code from timing
> -- remove op_info from struct msm_drm_private
> -- remove unnecessary wide_bus_en variables
> -- pass wide_bus_en into timing configuration by struct msm_dp
>
> Changes in v3:
> -- split patch into 3 patches
>
> Changes in v4:
> -- rework timing engine to not interfere with dsi/hdmi
> -- cover both widebus and compression
>
> Changes in v5:
> -- remove supports of DSI widebus and compression
>
> Changes in v7:
> -- split this patch into 3 patches
> -- add Tested-by
>
> Changes in v8:
> -- move new registers writes under DATA_HCTL_EN features check.
>
> Changes in v10:
> -- add const inside dpu_encoder_is_widebus_enabled()
> -- drop useless parenthesis please
>
> Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
> Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
next prev parent reply other threads:[~2022-02-25 18:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-23 0:27 [PATCH v10 0/4] drm/msm/dpu: enable widebus feature base on chip hardware revision Kuogee Hsieh
2022-02-23 0:27 ` [PATCH v10 1/4] drm/msm/dpu: adjust display_v_end for eDP and DP Kuogee Hsieh
2022-02-23 0:27 ` [PATCH v10 2/4] drm/msm/dpu: replace BIT(x) with correspond marco define string Kuogee Hsieh
2022-02-23 0:27 ` [PATCH v10 3/4] drm/msm/dpu: revise timing engine programming to support widebus feature Kuogee Hsieh
2022-02-25 18:13 ` Stephen Boyd [this message]
2022-02-23 0:27 ` [PATCH v10 4/4] drm/msm/dp: enable widebus feature for display port Kuogee Hsieh
2022-02-25 18:17 ` Stephen Boyd
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