From: Degdag Mohamed <degdagmohamed@gmail.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: freedreno@lists.freedesktop.org,
Bjorn Andersson <andersson@kernel.org>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
dri-devel@lists.freedesktop.org,
Stephen Boyd <swboyd@chromium.org>,
linux-arm-msm@vger.kernel.org,
Marijn Suijten <marijn.suijten@somainline.org>,
Sean Paul <sean@poorly.run>
Subject: Re: [PATCH 2/2] drm/msm/dsi: don't allow enabling 7nm VCO with unprogrammed rate
Date: Mon, 12 Jun 2023 06:04:17 +0100 [thread overview]
Message-ID: <CAEhjvduE+iMzzyC2Bex9C5=ueXE8NSZ6oGywRtAJv7gzyvbukw@mail.gmail.com> (raw)
In-Reply-To: <20230612031616.3620134-2-dmitry.baryshkov@linaro.org>
[Dmitry Baryshkov],
Thank you for sharing the patches. I have reviewed and tested all
three patches, and they seem to be working correctly.
Tested-by: Degdag Mohamed degdagmohamed@gmail.com
Please let me know if you need any further information or assistance.
Best regards,
Degdag Mohamed
On 6/12/23, Dmitry Baryshkov <dmitry.baryshkov@linaro.org> wrote:
> CCF can try enabling VCO before the rate has been programmed. This can
> cause clock lockups and/or other boot issues. Program the VCO to the
> minimal PLL rate if the read rate is 0 Hz.
>
> Reported-by: Degdag Mohamed <degdagmohamed@gmail.com>
> Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> index 3b1ed02f644d..6979d35eb7c3 100644
> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> @@ -395,11 +395,16 @@ static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm
> *pll)
> wmb(); /* Ensure that the reset is deasserted */
> }
>
> +static unsigned long dsi_pll_7nm_vco_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate);
> static int dsi_pll_7nm_vco_prepare(struct clk_hw *hw)
> {
> struct dsi_pll_7nm *pll_7nm = to_pll_7nm(hw);
> int rc;
>
> + if (dsi_pll_7nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0)
> + dsi_pll_7nm_vco_set_rate(hw, pll_7nm->phy->cfg->min_pll_rate,
> VCO_REF_CLK_RATE);
> +
> dsi_pll_enable_pll_bias(pll_7nm);
> if (pll_7nm->slave)
> dsi_pll_enable_pll_bias(pll_7nm->slave);
> --
> 2.39.2
>
>
next prev parent reply other threads:[~2023-06-12 7:30 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-12 3:16 [PATCH 1/2] drm/msm: provide fb_dirty implemenation Dmitry Baryshkov
2023-06-12 3:16 ` [PATCH 2/2] drm/msm/dsi: don't allow enabling 7nm VCO with unprogrammed rate Dmitry Baryshkov
2023-06-12 5:04 ` Degdag Mohamed [this message]
2023-06-12 9:15 ` Marijn Suijten
2023-06-12 9:21 ` Marijn Suijten
2023-06-12 18:30 ` Dmitry Baryshkov
2023-06-12 19:24 ` Marijn Suijten
2023-06-12 8:21 ` [PATCH 1/2] drm/msm: provide fb_dirty implemenation Thomas Zimmermann
2023-06-12 18:41 ` Dmitry Baryshkov
2023-06-12 9:14 ` Marijn Suijten
2023-06-12 10:48 ` Thomas Zimmermann
2023-06-12 18:31 ` Dmitry Baryshkov
2023-06-12 18:37 ` Marijn Suijten
2023-06-15 11:31 ` Dmitry Baryshkov
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