From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.4 required=3.0 tests=BAYES_00,DKIM_ADSP_CUSTOM_MED, DKIM_INVALID,DKIM_SIGNED,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MIME_HTML_MOSTLY,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B263EC433E0 for ; Sat, 13 Feb 2021 16:30:29 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C04F64E2C for ; Sat, 13 Feb 2021 16:30:29 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 3C04F64E2C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1504F898C0; Sat, 13 Feb 2021 16:30:28 +0000 (UTC) Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by gabe.freedesktop.org (Postfix) with ESMTPS id 004FA898C0 for ; Sat, 13 Feb 2021 16:30:25 +0000 (UTC) Received: by mail-wm1-x333.google.com with SMTP id o10so2248723wmc.1 for ; Sat, 13 Feb 2021 08:30:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=+xRJmgNnZI5oBoy/qOldulk8C27pru0CLldGbgzGjlE=; b=Ct7DasOzI9ms7VEv6ymzANVeKP4XPjrAASbNj9tFEOeqflRrLzBnHICv4RjjTd4z8S zyKWk5Xqw+zBs9SdToWV4w302Tt/5K6LdoFU9/bu2ALX4f8TUs8s3+MtVJihTg0iIPT1 cPq9mEdrcu78Xgfg6hihytVrl5i+zQCWmat7YjEyqu9PFFkvGPu6to/OBc4Z8zKKvXPR YcfA7tAEUexcQDMBVCxuFnGzBASG9aUmkvasz1NfwO8g0HpU0NAB1Q3lNcG3FbVc9zto V/pwf3PvbIvCmDBvdsM12OAwf5vedM98ow2f03VLRHpE6PI4kG8prQxO7f90Gjm9/GqU uzFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+xRJmgNnZI5oBoy/qOldulk8C27pru0CLldGbgzGjlE=; b=nYJrP8GfiKTccf4kmc5s+Ap0GrwPMhNvh6jhWJiCHhd2EuPFza8V8X5Xrb7lq51CEF oibMQ78/Uim2FL1AmywR88w8Wr7wxUpmu55H9jgmi48SRB+KYqKiRqCA+i1OP8UNSb7P 3gre76vSEU5l1jfAbkxcJfaBMLq/HgVdfbbuXjH42BIEbtpDdlRxz7+09wsXR17tNS2s FZCC1f0go/tI88FJrxPpLsM6UCBF8rMftgmA0SV8U6Xj2f/Ftfu7XxG3tZ7t7nPGnUVY btToykXJJeWqvTQAZuPRZGA467D3WltF/4Og9/rLyP4e8eCaab+cYd0J6krILc8n1n1e 1NLA== X-Gm-Message-State: AOAM532VZVKtkpyurQvBIv6RUbpXVx1fBjFaE4oJWxcLSVYk7qGlQ5ST 7GZLePipBzKIcrn+Kjp1ocrVJ6gFYwI5DLprSrg= X-Google-Smtp-Source: ABdhPJzwQrwu3ktt9jCT6CtfqJ9HPvGqfb5yJJw1Za4C4pw3RY9c79xV9Kn84HwGwMXnn7Q3/3LeeVfSiUEfacCUc54= X-Received: by 2002:a1c:3cd6:: with SMTP id j205mr7154447wma.166.1613233824393; Sat, 13 Feb 2021 08:30:24 -0800 (PST) MIME-Version: 1.0 References: <1609854367-2720-1-git-send-email-kevin3.tang@gmail.com> <1609854367-2720-5-git-send-email-kevin3.tang@gmail.com> In-Reply-To: From: Kevin Tang Date: Sun, 14 Feb 2021 00:30:12 +0800 Message-ID: Subject: Re: [PATCH v3 4/6] drm/sprd: add Unisoc's drm display controller driver To: Kevin Tang , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Rob Herring , Mark Rutland , Orson Zhai , Chunyan Zhang , "Linux-Kernel@Vger. Kernel. Org" , ML dri-devel , devicetree@vger.kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============1294752795==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1294752795== Content-Type: multipart/alternative; boundary="0000000000000af07a05bb3a457e" --0000000000000af07a05bb3a457e Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Daniel Vetter =E4=BA=8E2021=E5=B9=B42=E6=9C=883=E6=97=A5= =E5=91=A8=E4=B8=89 =E4=B8=8B=E5=8D=8810:15=E5=86=99=E9=81=93=EF=BC=9A > On Tue, Jan 05, 2021 at 09:46:05PM +0800, Kevin Tang wrote: > > Adds DPU(Display Processor Unit) support for the Unisoc's display > subsystem. > > It's support multi planes, scaler, rotation, PQ(Picture Quality) and > more. > > > > Cc: Orson Zhai > > Cc: Chunyan Zhang > > Signed-off-by: Kevin Tang > > > > v2: > > - Use drm_xxx to replace all DRM_XXX. > > - Use kzalloc to replace devm_kzalloc for sprd_dpu structure init. > > > > v3: > > - Remove dpu_layer stuff layer and commit layers by aotmic_update > > Scrolling through the code looks very tidy&neat, only thing I spotted is > that you could use the new drmm_ infrastructure we just landed. See > comments below, with that addressed: > Hi Daniel, Thank you for taking the time to review, i will update my patch on the drm-misc-next and replace drm_helpers with drmm_helpers. > > Acked-by: Daniel Vetter > > --- > > drivers/gpu/drm/sprd/Kconfig | 1 + > > drivers/gpu/drm/sprd/Makefile | 4 +- > > drivers/gpu/drm/sprd/sprd_dpu.c | 985 > ++++++++++++++++++++++++++++++++++++++++ > > drivers/gpu/drm/sprd/sprd_dpu.h | 120 +++++ > > drivers/gpu/drm/sprd/sprd_drm.c | 1 + > > drivers/gpu/drm/sprd/sprd_drm.h | 2 + > > 6 files changed, 1111 insertions(+), 2 deletions(-) > > create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.c > > create mode 100644 drivers/gpu/drm/sprd/sprd_dpu.h > > > > diff --git a/drivers/gpu/drm/sprd/Kconfig b/drivers/gpu/drm/sprd/Kconfi= g > > index 6e80cc9..9b4ef9a 100644 > > --- a/drivers/gpu/drm/sprd/Kconfig > > +++ b/drivers/gpu/drm/sprd/Kconfig > > @@ -3,6 +3,7 @@ config DRM_SPRD > > depends on ARCH_SPRD || COMPILE_TEST > > depends on DRM && OF > > select DRM_KMS_HELPER > > + select VIDEOMODE_HELPERS > > select DRM_GEM_CMA_HELPER > > select DRM_KMS_CMA_HELPER > > select DRM_MIPI_DSI > > diff --git a/drivers/gpu/drm/sprd/Makefile > b/drivers/gpu/drm/sprd/Makefile > > index 86d95d9..6c25bfa 100644 > > --- a/drivers/gpu/drm/sprd/Makefile > > +++ b/drivers/gpu/drm/sprd/Makefile > > @@ -1,5 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > > > -subdir-ccflags-y +=3D -I$(srctree)/$(src) > > +obj-y :=3D sprd_drm.o \ > > + sprd_dpu.o > > > > -obj-y :=3D sprd_drm.o > > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.c > b/drivers/gpu/drm/sprd/sprd_dpu.c > > new file mode 100644 > > index 0000000..d562d44 > > --- /dev/null > > +++ b/drivers/gpu/drm/sprd/sprd_dpu.c > > @@ -0,0 +1,985 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +/* > > + * Copyright (C) 2020 Unisoc Inc. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "sprd_drm.h" > > +#include "sprd_dpu.h" > > + > > +/* Global control registers */ > > +#define REG_DPU_CTRL 0x04 > > +#define REG_DPU_CFG0 0x08 > > +#define REG_PANEL_SIZE 0x20 > > +#define REG_BLEND_SIZE 0x24 > > +#define REG_BG_COLOR 0x2C > > + > > +/* Layer0 control registers */ > > +#define REG_LAY_BASE_ADDR0 0x30 > > +#define REG_LAY_BASE_ADDR1 0x34 > > +#define REG_LAY_BASE_ADDR2 0x38 > > +#define REG_LAY_CTRL 0x40 > > +#define REG_LAY_SIZE 0x44 > > +#define REG_LAY_PITCH 0x48 > > +#define REG_LAY_POS 0x4C > > +#define REG_LAY_ALPHA 0x50 > > +#define REG_LAY_CROP_START 0x5C > > + > > +/* Interrupt control registers */ > > +#define REG_DPU_INT_EN 0x1E0 > > +#define REG_DPU_INT_CLR 0x1E4 > > +#define REG_DPU_INT_STS 0x1E8 > > + > > +/* DPI control registers */ > > +#define REG_DPI_CTRL 0x1F0 > > +#define REG_DPI_H_TIMING 0x1F4 > > +#define REG_DPI_V_TIMING 0x1F8 > > + > > +/* MMU control registers */ > > +#define REG_MMU_EN 0x800 > > +#define REG_MMU_VPN_RANGE 0x80C > > +#define REG_MMU_VAOR_ADDR_RD 0x818 > > +#define REG_MMU_VAOR_ADDR_WR 0x81C > > +#define REG_MMU_INV_ADDR_RD 0x820 > > +#define REG_MMU_INV_ADDR_WR 0x824 > > +#define REG_MMU_PPN1 0x83C > > +#define REG_MMU_RANGE1 0x840 > > +#define REG_MMU_PPN2 0x844 > > +#define REG_MMU_RANGE2 0x848 > > + > > +/* Global control bits */ > > +#define BIT_DPU_RUN BIT(0) > > +#define BIT_DPU_STOP BIT(1) > > +#define BIT_DPU_REG_UPDATE BIT(2) > > +#define BIT_DPU_IF_EDPI BIT(0) > > + > > +/* Layer control bits */ > > +#define BIT_DPU_LAY_EN BIT(0) > > +#define BIT_DPU_LAY_LAYER_ALPHA (0x01 << 2) > > +#define BIT_DPU_LAY_COMBO_ALPHA (0x02 << 2) > > +#define BIT_DPU_LAY_FORMAT_YUV422_2PLANE (0x00 << 4) > > +#define BIT_DPU_LAY_FORMAT_YUV420_2PLANE (0x01 << 4) > > +#define BIT_DPU_LAY_FORMAT_YUV420_3PLANE (0x02 << 4) > > +#define BIT_DPU_LAY_FORMAT_ARGB8888 (0x03 << 4) > > +#define BIT_DPU_LAY_FORMAT_RGB565 (0x04 << 4) > > +#define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3 (0x00 << 8) > > +#define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0 (0x01 << 8) > > +#define BIT_DPU_LAY_NO_SWITCH (0x00 << 10) > > +#define BIT_DPU_LAY_RB_OR_UV_SWITCH (0x01 << 10) > > +#define BIT_DPU_LAY_MODE_BLEND_NORMAL (0x00 << 16) > > +#define BIT_DPU_LAY_MODE_BLEND_PREMULT (0x01 << 16) > > + > > +/* Interrupt control & status bits */ > > +#define BIT_DPU_INT_DONE BIT(0) > > +#define BIT_DPU_INT_TE BIT(1) > > +#define BIT_DPU_INT_ERR BIT(2) > > +#define BIT_DPU_INT_UPDATE_DONE BIT(4) > > +#define BIT_DPU_INT_VSYNC BIT(5) > > +#define BIT_DPU_INT_MMU_VAOR_RD BIT(16) > > +#define BIT_DPU_INT_MMU_VAOR_WR BIT(17) > > +#define BIT_DPU_INT_MMU_INV_RD BIT(18) > > +#define BIT_DPU_INT_MMU_INV_WR BIT(19) > > + > > +/* DPI control bits */ > > +#define BIT_DPU_EDPI_TE_EN BIT(8) > > +#define BIT_DPU_EDPI_FROM_EXTERNAL_PAD BIT(10) > > +#define BIT_DPU_DPI_HALT_EN BIT(16) > > + > > +static const u32 primary_fmts[] =3D { > > + DRM_FORMAT_XRGB8888, > > + DRM_FORMAT_XBGR8888, > > + DRM_FORMAT_ARGB8888, > > + DRM_FORMAT_ABGR8888, > > + DRM_FORMAT_RGBA8888, > > + DRM_FORMAT_BGRA8888, > > + DRM_FORMAT_RGBX8888, > > + DRM_FORMAT_RGB565, > > + DRM_FORMAT_BGR565, > > + DRM_FORMAT_NV12, > > + DRM_FORMAT_NV21, > > + DRM_FORMAT_NV16, > > + DRM_FORMAT_NV61, > > + DRM_FORMAT_YUV420, > > + DRM_FORMAT_YVU420, > > +}; > > + > > +struct sprd_plane { > > + struct drm_plane plane; > > + u32 index; > > +}; > > + > > +static inline struct sprd_plane *to_sprd_plane(struct drm_plane *plane= ) > > +{ > > + return container_of(plane, struct sprd_plane, plane); > > +} > > + > > +static u32 check_mmu_isr(struct sprd_dpu *dpu, u32 reg_val) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + u32 mmu_mask =3D BIT_DPU_INT_MMU_VAOR_RD | > > + BIT_DPU_INT_MMU_VAOR_WR | > > + BIT_DPU_INT_MMU_INV_RD | > > + BIT_DPU_INT_MMU_INV_WR; > > + u32 val =3D reg_val & mmu_mask; > > + int i; > > + > > + if (val) { > > + drm_err(dpu->drm, "--- iommu interrupt err: 0x%04x ---\n"= , > val); > > + > > + if (val & BIT_DPU_INT_MMU_INV_RD) > > + drm_err(dpu->drm, "iommu invalid read error, addr= : > 0x%08x\n", > > + readl(ctx->base + REG_MMU_INV_ADDR_RD)); > > + if (val & BIT_DPU_INT_MMU_INV_WR) > > + drm_err(dpu->drm, "iommu invalid write error, > addr: 0x%08x\n", > > + readl(ctx->base + REG_MMU_INV_ADDR_WR)); > > + if (val & BIT_DPU_INT_MMU_VAOR_RD) > > + drm_err(dpu->drm, "iommu va out of range read > error, addr: 0x%08x\n", > > + readl(ctx->base + REG_MMU_VAOR_ADDR_RD)); > > + if (val & BIT_DPU_INT_MMU_VAOR_WR) > > + drm_err(dpu->drm, "iommu va out of range write > error, addr: 0x%08x\n", > > + readl(ctx->base + REG_MMU_VAOR_ADDR_WR)); > > + > > + for (i =3D 0; i < 8; i++) { > > + reg_val =3D layer_reg_rd(ctx, REG_LAY_CTRL, i); > > + if (reg_val & 0x1) > > + drm_info(dpu->drm, "layer%d: 0x%08x 0x%08= x > 0x%08x ctrl: 0x%08x\n", i, > > + layer_reg_rd(ctx, > REG_LAY_BASE_ADDR0, i), > > + layer_reg_rd(ctx, > REG_LAY_BASE_ADDR1, i), > > + layer_reg_rd(ctx, > REG_LAY_BASE_ADDR2, i), > > + layer_reg_rd(ctx, REG_LAY_CTRL, > i)); > > + } > > + } > > + > > + return val; > > +} > > + > > +static int dpu_wait_stop_done(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + int rc; > > + > > + if (ctx->stopped) > > + return 0; > > + > > + rc =3D wait_event_interruptible_timeout(ctx->wait_queue, > ctx->evt_stop, > > + msecs_to_jiffies(500)); > > + ctx->evt_stop =3D false; > > + > > + ctx->stopped =3D true; > > + > > + if (!rc) { > > + drm_err(dpu->drm, "dpu wait for stop done time out!\n"); > > + return -ETIMEDOUT; > > + } > > + > > + return 0; > > +} > > + > > +static int dpu_wait_update_done(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + int rc; > > + > > + ctx->evt_update =3D false; > > + > > + rc =3D wait_event_interruptible_timeout(ctx->wait_queue, > ctx->evt_update, > > + msecs_to_jiffies(500)); > > + > > + if (!rc) { > > + drm_err(dpu->drm, "dpu wait for reg update done time > out!\n"); > > + return -ETIMEDOUT; > > + } > > + > > + return 0; > > +} > > + > > +static u32 drm_format_to_dpu(struct drm_framebuffer *fb) > > +{ > > + u32 format =3D 0; > > + > > + switch (fb->format->format) { > > + case DRM_FORMAT_BGRA8888: > > + /* BGRA8888 -> ARGB8888 */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0; > > + format |=3D BIT_DPU_LAY_FORMAT_ARGB8888; > > + break; > > + case DRM_FORMAT_RGBX8888: > > + case DRM_FORMAT_RGBA8888: > > + /* RGBA8888 -> ABGR8888 */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0; > > + /* fallthrough */ > > + case DRM_FORMAT_ABGR8888: > > + /* RB switch */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + /* fallthrough */ > > + case DRM_FORMAT_ARGB8888: > > + format |=3D BIT_DPU_LAY_FORMAT_ARGB8888; > > + break; > > + case DRM_FORMAT_XBGR8888: > > + /* RB switch */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + /* fallthrough */ > > + case DRM_FORMAT_XRGB8888: > > + format |=3D BIT_DPU_LAY_FORMAT_ARGB8888; > > + break; > > + case DRM_FORMAT_BGR565: > > + /* RB switch */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + /* fallthrough */ > > + case DRM_FORMAT_RGB565: > > + format |=3D BIT_DPU_LAY_FORMAT_RGB565; > > + break; > > + case DRM_FORMAT_NV12: > > + /* 2-Lane: Yuv420 */ > > + format |=3D BIT_DPU_LAY_FORMAT_YUV420_2PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_NO_SWITCH; > > + break; > > + case DRM_FORMAT_NV21: > > + /* 2-Lane: Yuv420 */ > > + format |=3D BIT_DPU_LAY_FORMAT_YUV420_2PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + break; > > + case DRM_FORMAT_NV16: > > + /* 2-Lane: Yuv422 */ > > + format |=3D BIT_DPU_LAY_FORMAT_YUV422_2PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + break; > > + case DRM_FORMAT_NV61: > > + /* 2-Lane: Yuv422 */ > > + format |=3D BIT_DPU_LAY_FORMAT_YUV422_2PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_NO_SWITCH; > > + break; > > + case DRM_FORMAT_YUV420: > > + format |=3D BIT_DPU_LAY_FORMAT_YUV420_3PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_NO_SWITCH; > > + break; > > + case DRM_FORMAT_YVU420: > > + format |=3D BIT_DPU_LAY_FORMAT_YUV420_3PLANE; > > + /* Y endian */ > > + format |=3D BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3; > > + /* UV endian */ > > + format |=3D BIT_DPU_LAY_RB_OR_UV_SWITCH; > > + break; > > + default: > > + break; > > + } > > + > > + return format; > > +} > > + > > +static u32 drm_rotation_to_dpu(struct drm_plane_state *state) > > +{ > > + u32 rotation; > > + > > + switch (state->rotation) { > > + default: > > + case DRM_MODE_ROTATE_0: > > + rotation =3D DPU_LAYER_ROTATION_0; > > + break; > > + case DRM_MODE_ROTATE_90: > > + rotation =3D DPU_LAYER_ROTATION_90; > > + break; > > + case DRM_MODE_ROTATE_180: > > + rotation =3D DPU_LAYER_ROTATION_180; > > + break; > > + case DRM_MODE_ROTATE_270: > > + rotation =3D DPU_LAYER_ROTATION_270; > > + break; > > + case DRM_MODE_REFLECT_Y: > > + rotation =3D DPU_LAYER_ROTATION_180_M; > > + break; > > + case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90): > > + rotation =3D DPU_LAYER_ROTATION_90_M; > > + break; > > + case DRM_MODE_REFLECT_X: > > + rotation =3D DPU_LAYER_ROTATION_0_M; > > + break; > > + case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90): > > + rotation =3D DPU_LAYER_ROTATION_270_M; > > + break; > > + } > > + > > + return rotation; > > +} > > + > > +static u32 drm_blend_to_dpu(struct drm_plane_state *state) > > +{ > > + u32 blend =3D 0; > > + > > + switch (state->pixel_blend_mode) { > > + case DRM_MODE_BLEND_COVERAGE: > > + /* alpha mode select - combo alpha */ > > + blend |=3D BIT_DPU_LAY_COMBO_ALPHA; > > + /* Normal mode */ > > + blend |=3D BIT_DPU_LAY_MODE_BLEND_NORMAL; > > + break; > > + case DRM_MODE_BLEND_PREMULTI: > > + /* alpha mode select - combo alpha */ > > + blend |=3D BIT_DPU_LAY_COMBO_ALPHA; > > + /* Pre-mult mode */ > > + blend |=3D BIT_DPU_LAY_MODE_BLEND_PREMULT; > > + break; > > + case DRM_MODE_BLEND_PIXEL_NONE: > > + default: > > + /* don't do blending, maybe RGBX */ > > + /* alpha mode select - layer alpha */ > > + blend |=3D BIT_DPU_LAY_LAYER_ALPHA; > > + break; > > + } > > + > > + return blend; > > +} > > + > > +static void sprd_dpu_layer(struct sprd_dpu *dpu, struct sprd_plane > *plane, > > + struct drm_plane_state *state) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + struct drm_gem_cma_object *cma_obj; > > + const struct drm_format_info *info; > > + struct drm_framebuffer *fb =3D state->fb; > > + u32 addr, size, offset, pitch, blend, format, rotation; > > + u32 src_x =3D state->src_x >> 16; > > + u32 src_y =3D state->src_y >> 16; > > + u32 src_w =3D state->src_w >> 16; > > + u32 src_h =3D state->src_h >> 16; > > + u32 dst_x =3D state->crtc_x; > > + u32 dst_y =3D state->crtc_y; > > + u32 alpha =3D state->alpha; > > + int i; > > + > > + offset =3D (dst_x & 0xffff) | (dst_y << 16); > > + size =3D (src_w & 0xffff) | (src_h << 16); > > + > > + for (i =3D 0; i < fb->format->num_planes; i++) { > > + cma_obj =3D drm_fb_cma_get_gem_obj(fb, i); > > + addr =3D cma_obj->paddr + fb->offsets[i]; > > + > > + if (i =3D=3D 0) > > + layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, > plane->index); > > + else if (i =3D=3D 1) > > + layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, > plane->index); > > + else > > + layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, > plane->index); > > + } > > + > > + info =3D drm_format_info(fb->format->format); > > + if (fb->format->num_planes =3D=3D 3) { > > + /* UV pitch is 1/2 of Y pitch */ > > + pitch =3D (fb->pitches[0] / info->cpp[0]) | > > + (fb->pitches[0] / info->cpp[0] << 15); > > + } else { > > + pitch =3D fb->pitches[0] / info->cpp[0]; > > + } > > + > > + layer_reg_wr(ctx, REG_LAY_POS, offset, plane->index); > > + layer_reg_wr(ctx, REG_LAY_SIZE, size, plane->index); > > + layer_reg_wr(ctx, REG_LAY_CROP_START, > > + src_y << 16 | src_x, plane->index); > > + layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, plane->index); > > + layer_reg_wr(ctx, REG_LAY_PITCH, pitch, plane->index); > > + > > + format =3D drm_format_to_dpu(fb); > > + blend =3D drm_blend_to_dpu(state); > > + rotation =3D drm_rotation_to_dpu(state); > > + > > + layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN | > > + format | > > + blend | > > + rotation << 20, > > + plane->index); > > +} > > + > > +static void sprd_dpu_flip(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + u32 reg_val; > > + > > + /* > > + * Make sure the dpu is in stop status. DPU has no shadow > > + * registers in EDPI mode. So the config registers can only be > > + * updated in the rising edge of DPU_RUN bit. > > + */ > > + if (ctx->if_type =3D=3D SPRD_DPU_IF_EDPI) > > + dpu_wait_stop_done(dpu); > > + > > + /* update trigger and wait */ > > + if (ctx->if_type =3D=3D SPRD_DPU_IF_DPI) { > > + if (!ctx->stopped) { > > + dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE= ); > > + dpu_wait_update_done(dpu); > > + } > > + > > + dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR); > > + } else if (ctx->if_type =3D=3D SPRD_DPU_IF_EDPI) { > > + dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN); > > + > > + ctx->stopped =3D false; > > + } > > + > > + /* > > + * If the following interrupt was disabled in isr, > > + * re-enable it. > > + */ > > + reg_val =3D BIT_DPU_INT_MMU_VAOR_RD | > > + BIT_DPU_INT_MMU_VAOR_WR | > > + BIT_DPU_INT_MMU_INV_RD | > > + BIT_DPU_INT_MMU_INV_WR; > > + dpu_reg_set(ctx, REG_DPU_INT_EN, reg_val); > > +} > > + > > +static void sprd_dpu_init(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + u32 reg_val, size; > > + > > + writel(0x00, ctx->base + REG_BG_COLOR); > > + > > + size =3D (ctx->vm.vactive << 16) | ctx->vm.hactive; > > + writel(size, ctx->base + REG_PANEL_SIZE); > > + writel(size, ctx->base + REG_BLEND_SIZE); > > + > > + writel(0x00, ctx->base + REG_MMU_EN); > > + writel(0x00, ctx->base + REG_MMU_PPN1); > > + writel(0xffff, ctx->base + REG_MMU_RANGE1); > > + writel(0x00, ctx->base + REG_MMU_PPN2); > > + writel(0xffff, ctx->base + REG_MMU_RANGE2); > > + writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE); > > +} > > + > > +static void sprd_dpu_fini(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + > > + writel(0x00, ctx->base + REG_DPU_INT_EN); > > + writel(0xff, ctx->base + REG_DPU_INT_CLR); > > +} > > + > > +static void sprd_dpi_init(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + u32 int_mask =3D 0; > > + u32 reg_val; > > + > > + if (ctx->if_type =3D=3D SPRD_DPU_IF_DPI) { > > + /* use dpi as interface */ > > + dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI); > > + /* disable Halt function for SPRD DSI */ > > + dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN); > > + /* select te from external pad */ > > + dpu_reg_set(ctx, REG_DPI_CTRL, > BIT_DPU_EDPI_FROM_EXTERNAL_PAD); > > + > > + /* set dpi timing */ > > + reg_val =3D ctx->vm.hsync_len << 0 | > > + ctx->vm.hback_porch << 8 | > > + ctx->vm.hfront_porch << 20; > > + writel(reg_val, ctx->base + REG_DPI_H_TIMING); > > + > > + reg_val =3D ctx->vm.vsync_len << 0 | > > + ctx->vm.vback_porch << 8 | > > + ctx->vm.vfront_porch << 20; > > + writel(reg_val, ctx->base + REG_DPI_V_TIMING); > > + > > + if (ctx->vm.vsync_len + ctx->vm.vback_porch < 32) > > + drm_warn(dpu->drm, "Warning: (vsync + vbp) < 32, = " > > + "underflow risk!\n"); > > + > > + /* enable dpu update done INT */ > > + int_mask |=3D BIT_DPU_INT_UPDATE_DONE; > > + /* enable dpu done INT */ > > + int_mask |=3D BIT_DPU_INT_DONE; > > + /* enable dpu dpi vsync */ > > + int_mask |=3D BIT_DPU_INT_VSYNC; > > + /* enable dpu TE INT */ > > + int_mask |=3D BIT_DPU_INT_TE; > > + /* enable underflow err INT */ > > + int_mask |=3D BIT_DPU_INT_ERR; > > + } else if (ctx->if_type =3D=3D SPRD_DPU_IF_EDPI) { > > + /* use edpi as interface */ > > + dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI); > > + /* use external te */ > > + dpu_reg_set(ctx, REG_DPI_CTRL, > BIT_DPU_EDPI_FROM_EXTERNAL_PAD); > > + /* enable te */ > > + dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN); > > + > > + /* enable stop done INT */ > > + int_mask |=3D BIT_DPU_INT_DONE; > > + /* enable TE INT */ > > + int_mask |=3D BIT_DPU_INT_TE; > > + } > > + > > + /* enable iommu va out of range read error INT */ > > + int_mask |=3D BIT_DPU_INT_MMU_VAOR_RD; > > + /* enable iommu va out of range write error INT */ > > + int_mask |=3D BIT_DPU_INT_MMU_VAOR_WR; > > + /* enable iommu invalid read error INT */ > > + int_mask |=3D BIT_DPU_INT_MMU_INV_RD; > > + /* enable iommu invalid write error INT */ > > + int_mask |=3D BIT_DPU_INT_MMU_INV_WR; > > + > > + writel(int_mask, ctx->base + REG_DPU_INT_EN); > > +} > > + > > +void sprd_dpu_run(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + > > + dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN); > > + > > + ctx->stopped =3D false; > > +} > > + > > +void sprd_dpu_stop(struct sprd_dpu *dpu) > > +{ > > + struct dpu_context *ctx =3D &dpu->ctx; > > + > > + if (ctx->if_type =3D=3D SPRD_DPU_IF_DPI) > > + dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP); > > + > > + dpu_wait_stop_done(dpu); > > +} > > + > > +static int sprd_plane_atomic_check(struct drm_plane *plane, > > + struct drm_plane_state *state) > > +{ > > + struct drm_framebuffer *fb =3D state->fb; > > + struct drm_crtc_state *crtc_state; > > + u32 fmt; > > + > > + if (!fb || !state->crtc) > > + return 0; > > + > > + fmt =3D drm_format_to_dpu(fb); > > + if (!fmt) > > + return -EINVAL; > > + > > + crtc_state =3D drm_atomic_get_crtc_state(state->state, state->crt= c); > > + if (IS_ERR(crtc_state)) > > + return PTR_ERR(crtc_state); > > + > > + return drm_atomic_helper_check_plane_state(state, crtc_state, > > + > DRM_PLANE_HELPER_NO_SCALING, > > + > DRM_PLANE_HELPER_NO_SCALING, > > + true, true); > > +} > > + > > +static void sprd_plane_atomic_update(struct drm_plane *plane, > > + struct drm_plane_state *old_state) > > +{ > > + struct drm_plane_state *state =3D plane->state; > > + struct sprd_plane *p =3D to_sprd_plane(plane); > > + struct sprd_dpu *dpu =3D to_sprd_crtc(state->crtc); > > + > > + /* start configure dpu layers */ > > + sprd_dpu_layer(dpu, p, state); > > +} > > + > > +static void sprd_plane_atomic_disable(struct drm_plane *plane, > > + struct drm_plane_state *old_state) > > +{ > > + struct sprd_plane *p =3D to_sprd_plane(plane); > > + struct sprd_dpu *dpu =3D to_sprd_crtc(old_state->crtc); > > + > > + layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, p->index); > > +} > > + > > +static void sprd_plane_create_properties(struct sprd_plane *p, int > index) > > +{ > > + unsigned int supported_modes =3D BIT(DRM_MODE_BLEND_PIXEL_NONE) | > > + BIT(DRM_MODE_BLEND_PREMULTI) | > > + BIT(DRM_MODE_BLEND_COVERAGE); > > + > > + /* create rotation property */ > > + drm_plane_create_rotation_property(&p->plane, > > + DRM_MODE_ROTATE_0, > > + DRM_MODE_ROTATE_MASK | > > + DRM_MODE_REFLECT_MASK); > > + > > + /* create alpha property */ > > + drm_plane_create_alpha_property(&p->plane); > > + > > + /* create blend mode property */ > > + drm_plane_create_blend_mode_property(&p->plane, supported_modes); > > + > > + /* create zpos property */ > > + drm_plane_create_zpos_immutable_property(&p->plane, index); > > +} > > + > > +static const struct drm_plane_helper_funcs sprd_plane_helper_funcs =3D= { > > + .atomic_check =3D sprd_plane_atomic_check, > > + .atomic_update =3D sprd_plane_atomic_update, > > + .atomic_disable =3D sprd_plane_atomic_disable, > > +}; > > + > > +static const struct drm_plane_funcs sprd_plane_funcs =3D { > > + .update_plane =3D drm_atomic_helper_update_plane, > > + .disable_plane =3D drm_atomic_helper_disable_plane, > > + .destroy =3D drm_plane_cleanup, > > + .reset =3D drm_atomic_helper_plane_reset, > > + .atomic_duplicate_state =3D drm_atomic_helper_plane_duplicate_sta= te, > > + .atomic_destroy_state =3D drm_atomic_helper_plane_destroy_state, > > +}; > > + > > +static struct drm_plane *sprd_plane_init(struct drm_device *drm, > > + struct sprd_dpu *dpu) > > +{ > > + struct drm_plane *primary =3D NULL; > > + struct sprd_plane *p =3D NULL; > > + int ret, i; > > + > > + for (i =3D 0; i < 6; i++) { > > + p =3D devm_kzalloc(drm->dev, sizeof(*p), GFP_KERNEL); > > You still have a devm_kzalloc here. We've just landed some neat new drmm_ > helpers to allocate planes, please use these instead. See > drmm_universal_plane_alloc(). > Got it! > > > + if (!p) > > + return ERR_PTR(-ENOMEM); > > + > > + ret =3D drm_universal_plane_init(drm, &p->plane, 1, > > + &sprd_plane_funcs, > primary_fmts, > > + ARRAY_SIZE(primary_fmts), > NULL, > > + DRM_PLANE_TYPE_PRIMARY, > NULL); > > + if (ret) { > > + drm_err(drm, "fail to init primary plane\n"); > > + return ERR_PTR(ret); > > + } > > + > > + drm_plane_helper_add(&p->plane, &sprd_plane_helper_funcs)= ; > > + > > + sprd_plane_create_properties(p, i); > > + > > + p->index =3D i; > > + if (i =3D=3D 0) > > + primary =3D &p->plane; > > + } > > + > > + return primary; > > +} > > + > > +static enum drm_mode_status sprd_crtc_mode_valid(struct drm_crtc *crtc= , > > + const struct drm_display_mode > *mode) > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + > > + drm_dbg(dpu->drm, "%s() mode: "DRM_MODE_FMT"\n", __func__, > DRM_MODE_ARG(mode)); > > + > > + if (mode->type & DRM_MODE_TYPE_PREFERRED) { > > + drm_display_mode_to_videomode(mode, &dpu->ctx.vm); > > + > > + if ((mode->hdisplay =3D=3D mode->htotal) || > > + (mode->vdisplay =3D=3D mode->vtotal)) > > + dpu->ctx.if_type =3D SPRD_DPU_IF_EDPI; > > + else > > + dpu->ctx.if_type =3D SPRD_DPU_IF_DPI; > > + } > > + > > + return MODE_OK; > > +} > > + > > +static void sprd_crtc_atomic_enable(struct drm_crtc *crtc, > > + struct drm_crtc_state *old_state) > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + > > + sprd_dpu_init(dpu); > > + > > + sprd_dpi_init(dpu); > > + > > + enable_irq(dpu->ctx.irq); > > + > > + drm_crtc_vblank_on(&dpu->crtc); > > +} > > + > > +static void sprd_crtc_atomic_disable(struct drm_crtc *crtc, > > + struct drm_crtc_state *old_state) > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + struct drm_device *drm =3D dpu->crtc.dev; > > + > > + drm_crtc_vblank_off(&dpu->crtc); > > + > > + disable_irq(dpu->ctx.irq); > > + > > + sprd_dpu_fini(dpu); > > + > > + spin_lock_irq(&drm->event_lock); > > + if (crtc->state->event) { > > + drm_crtc_send_vblank_event(crtc, crtc->state->event); > > + crtc->state->event =3D NULL; > > + } > > + spin_unlock_irq(&drm->event_lock); > > +} > > + > > +static int sprd_crtc_atomic_check(struct drm_crtc *crtc, > > + struct drm_crtc_state *state) > > +{ > > + drm_dbg(crtc->dev, "%s()\n", __func__); > > + > > + return 0; > > +} > > + > > +static void sprd_crtc_atomic_flush(struct drm_crtc *crtc, > > + struct drm_crtc_state *old_state) > > + > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + struct drm_device *drm =3D dpu->crtc.dev; > > + > > + sprd_dpu_flip(dpu); > > + > > + spin_lock_irq(&drm->event_lock); > > + if (crtc->state->event) { > > + drm_crtc_send_vblank_event(crtc, crtc->state->event); > > + crtc->state->event =3D NULL; > > + } > > + spin_unlock_irq(&drm->event_lock); > > +} > > + > > +static int sprd_crtc_enable_vblank(struct drm_crtc *crtc) > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + > > + dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC); > > + > > + return 0; > > +} > > + > > +static void sprd_crtc_disable_vblank(struct drm_crtc *crtc) > > +{ > > + struct sprd_dpu *dpu =3D to_sprd_crtc(crtc); > > + > > + dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC); > > +} > > + > > +static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs =3D { > > + .mode_valid =3D sprd_crtc_mode_valid, > > + .atomic_check =3D sprd_crtc_atomic_check, > > + .atomic_flush =3D sprd_crtc_atomic_flush, > > + .atomic_enable =3D sprd_crtc_atomic_enable, > > + .atomic_disable =3D sprd_crtc_atomic_disable, > > +}; > > + > > +static const struct drm_crtc_funcs sprd_crtc_funcs =3D { > > + .destroy =3D drm_crtc_cleanup, > > + .set_config =3D drm_atomic_helper_set_config, > > + .page_flip =3D drm_atomic_helper_page_flip, > > + .reset =3D drm_atomic_helper_crtc_reset, > > + .atomic_duplicate_state =3D drm_atomic_helper_crtc_duplicate_stat= e, > > + .atomic_destroy_state =3D drm_atomic_helper_crtc_destroy_state, > > + .enable_vblank =3D sprd_crtc_enable_vblank, > > + .disable_vblank =3D sprd_crtc_disable_vblank, > > +}; > > + > > +static int sprd_crtc_init(struct drm_device *drm, struct drm_crtc *crt= c, > > + struct drm_plane *primary) > > +{ > > + struct device_node *port; > > + int ret; > > + > > + /* > > + * set crtc port so that drm_of_find_possible_crtcs call works > > + */ > > + port =3D of_parse_phandle(drm->dev->of_node, "ports", 0); > > + if (!port) { > > + drm_err(drm, "find 'ports' phandle of %s failed\n", > > + drm->dev->of_node->full_name); > > + return -EINVAL; > > + } > > + of_node_put(port); > > + crtc->port =3D port; > > + > > + ret =3D drm_crtc_init_with_planes(drm, crtc, primary, NULL, > > + &sprd_crtc_funcs, NULL); > > + if (ret) { > > + drm_err(drm, "failed to init crtc.\n"); > > + return ret; > > + } > > + > > + drm_crtc_helper_add(crtc, &sprd_crtc_helper_funcs); > > + > > + return 0; > > +} > > + > > +static irqreturn_t sprd_dpu_isr(int irq, void *data) > > +{ > > + struct sprd_dpu *dpu =3D data; > > + struct dpu_context *ctx =3D &dpu->ctx; > > + u32 reg_val, int_mask =3D 0; > > + > > + reg_val =3D readl(ctx->base + REG_DPU_INT_STS); > > + > > + /* disable err interrupt */ > > + if (reg_val & BIT_DPU_INT_ERR) { > > + int_mask |=3D BIT_DPU_INT_ERR; > > + drm_warn(dpu->drm, "Warning: dpu underflow!\n"); > > + } > > + > > + /* dpu update done isr */ > > + if (reg_val & BIT_DPU_INT_UPDATE_DONE) { > > + ctx->evt_update =3D true; > > + wake_up_interruptible_all(&ctx->wait_queue); > > + } > > + > > + /* dpu stop done isr */ > > + if (reg_val & BIT_DPU_INT_DONE) { > > + ctx->evt_stop =3D true; > > + wake_up_interruptible_all(&ctx->wait_queue); > > + } > > + > > + if (reg_val & BIT_DPU_INT_VSYNC) > > + drm_crtc_handle_vblank(&dpu->crtc); > > + > > + int_mask |=3D check_mmu_isr(dpu, reg_val); > > + > > + writel(reg_val, ctx->base + REG_DPU_INT_CLR); > > + dpu_reg_clr(ctx, REG_DPU_INT_EN, int_mask); > > + > > + return IRQ_HANDLED; > > +} > > + > > +static int sprd_dpu_bind(struct device *dev, struct device *master, > void *data) > > +{ > > + struct drm_device *drm =3D data; > > + struct sprd_dpu *dpu =3D dev_get_drvdata(dev); > > + struct drm_plane *plane; > > + int ret; > > + > > + plane =3D sprd_plane_init(drm, dpu); > > + if (IS_ERR_OR_NULL(plane)) { > > + ret =3D PTR_ERR(plane); > > + return ret; > > + } > > + > > + ret =3D sprd_crtc_init(drm, &dpu->crtc, plane); > > + if (ret) > > + return ret; > > + > > + dpu->drm =3D drm; > > + > > + return 0; > > +} > > + > > +static void sprd_dpu_unbind(struct device *dev, struct device *master, > > + void *data) > > +{ > > + struct sprd_dpu *dpu =3D dev_get_drvdata(dev); > > + > > + drm_crtc_cleanup(&dpu->crtc); > > +} > > + > > +static const struct component_ops dpu_component_ops =3D { > > + .bind =3D sprd_dpu_bind, > > + .unbind =3D sprd_dpu_unbind, > > +}; > > + > > +static int sprd_dpu_context_init(struct sprd_dpu *dpu, > > + struct device *dev) > > +{ > > + struct platform_device *pdev =3D to_platform_device(dev); > > + struct dpu_context *ctx =3D &dpu->ctx; > > + struct resource *res; > > + int ret; > > + > > + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + ctx->base =3D devm_ioremap(dev, res->start, resource_size(res)); > > + if (!ctx->base) { > > + dev_err(dev, "failed to map dpu registers\n"); > > + return -EFAULT; > > + } > > + > > + ctx->irq =3D platform_get_irq(pdev, 0); > > + if (ctx->irq < 0) { > > + dev_err(dev, "failed to get dpu irq\n"); > > + return ctx->irq; > > + } > > + > > + irq_set_status_flags(ctx->irq, IRQ_NOAUTOEN); > > + ret =3D devm_request_irq(dev, ctx->irq, sprd_dpu_isr, > > + 0, "DPU", dpu); > > + if (ret) { > > + dev_err(dev, "failed to register dpu irq handler\n"); > > + return ret; > > + } > > + > > + init_waitqueue_head(&ctx->wait_queue); > > + > > + return 0; > > +} > > + > > +static const struct of_device_id dpu_match_table[] =3D { > > + { .compatible =3D "sprd,sharkl3-dpu" }, > > + { /* sentinel */ }, > > +}; > > + > > +static int sprd_dpu_probe(struct platform_device *pdev) > > +{ > > + struct sprd_dpu *dpu; > > + int ret; > > + > > + dpu =3D kzalloc(sizeof(*dpu), GFP_KERNEL); > > + if (!dpu) > > + return -ENOMEM; > > + > > + ret =3D sprd_dpu_context_init(dpu, &pdev->dev); > > + if (ret) { > > + kfree(dpu); > > + return ret; > > + } > > + > > + platform_set_drvdata(pdev, dpu); > > The above should be moved into your bind function, with that you can > allocate the struct sprd_dpu with drmm_crtc_alloc_with_planes() and remov= e > a bunch of cleanup code. > Got it, it seems unbind ops(drm_crtc_cleanup) is also no need here. > > + > > + return component_add(&pdev->dev, &dpu_component_ops); > > +} > > + > > +static int sprd_dpu_remove(struct platform_device *pdev) > > +{ > > + struct sprd_dpu *dpu =3D platform_get_drvdata(pdev); > > + > > + component_del(&pdev->dev, &dpu_component_ops); > > + > > + kfree(dpu); > > The kfree here is wrong, you'd need to hook into the ->destroy hook of th= e > drm_crtc_funcs, but if you're using drmm_ like suggested above it should > all work including driver unload and any ordering issues with > deferred_probe. > Got it! > > > + return 0; > > +} > > + > > +struct platform_driver sprd_dpu_driver =3D { > > + .probe =3D sprd_dpu_probe, > > + .remove =3D sprd_dpu_remove, > > + .driver =3D { > > + .name =3D "sprd-dpu-drv", > > + .of_match_table =3D dpu_match_table, > > + }, > > +}; > > + > > +MODULE_AUTHOR("Leon He "); > > +MODULE_AUTHOR("Kevin Tang "); > > +MODULE_DESCRIPTION("Unisoc Display Controller Driver"); > > +MODULE_LICENSE("GPL v2"); > > diff --git a/drivers/gpu/drm/sprd/sprd_dpu.h > b/drivers/gpu/drm/sprd/sprd_dpu.h > > new file mode 100644 > > index 0000000..a937ba1 > > --- /dev/null > > +++ b/drivers/gpu/drm/sprd/sprd_dpu.h > > @@ -0,0 +1,120 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright (C) 2020 Unisoc Inc. > > + */ > > + > > +#ifndef __SPRD_DPU_H__ > > +#define __SPRD_DPU_H__ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include