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From: Hsin-Yi Wang <hsinyi@chromium.org>
To: CK Hu <ck.hu@mediatek.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Devicetree List <devicetree@vger.kernel.org>,
	David Airlie <airlied@linux.ie>,
	lkml <linux-kernel@vger.kernel.org>,
	dri-devel <dri-devel@lists.freedesktop.org>,
	Yongqiang Niu <yongqiang.niu@mediatek.com>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v12 6/8] drm/mediatek: enable dither function
Date: Fri, 29 Jan 2021 14:24:18 +0800	[thread overview]
Message-ID: <CAJMQK-gKKjLJ5xOAKOx5BM5dL2MxgFq72FVCfGTfzK4ZXzRJfA@mail.gmail.com> (raw)
In-Reply-To: <1611883982.5226.12.camel@mtksdaap41>

On Fri, Jan 29, 2021 at 9:33 AM CK Hu <ck.hu@mediatek.com> wrote:
>
> Hi, Hsin-Yi:
>
> On Thu, 2021-01-28 at 19:23 +0800, Hsin-Yi Wang wrote:
> > From: Yongqiang Niu <yongqiang.niu@mediatek.com>
> >
> > for 5 or 6 bpc panel, we need enable dither function
> > to improve the display quality
> >
> > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> > Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> > ---
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 15 +++++++++++++--
> >  1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index ac2cb25620357..6c8f246380a74 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -53,6 +53,7 @@
> >  #define DITHER_EN                            BIT(0)
> >  #define DISP_DITHER_CFG                              0x0020
> >  #define DITHER_RELAY_MODE                    BIT(0)
> > +#define DITHER_ENGINE_EN                     BIT(1)
> >  #define DISP_DITHER_SIZE                     0x0030
> >
> >  #define LUT_10BIT_MASK                               0x03ff
> > @@ -314,9 +315,19 @@ static void mtk_dither_config(struct device *dev, unsigned int w,
> >                             unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> >  {
> >       struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
> > +     bool enable = (bpc == 5 || bpc == 6);
>
> I strongly believe that dither function in dither is identical to the
> one in gamma and od, and in mtk_dither_set_common(), 'bpc >=
> MTK_MIN_BPC' is valid, so I believe we need not to limit bpc to 5 or 6.
> But we should consider the case that bpc is invalid in
> mtk_dither_set_common(). Invalid case in gamma and od use different way
> to process. For gamma, dither is default relay mode, so invalid bpc
> would do nothing in mtk_dither_set_common() and result in relay mode.
> For od, it set to relay mode first, them invalid bpc would do nothing in
> mtk_dither_set_common() and result in relay mode. I would like dither,
> gamma and od to process invalid bpc in the same way. One solution is to
> set relay mode in mtk_dither_set_common() for invalid bpc.
>
> Regards,
> CK
>

I modify the mtk_dither_config() to follow:


diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ac2cb25620357..5b7fcedb9f9a8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -53,6 +53,7 @@
 #define DITHER_EN                              BIT(0)
 #define DISP_DITHER_CFG                                0x0020
 #define DITHER_RELAY_MODE                      BIT(0)
+#define DITHER_ENGINE_EN                       BIT(1)
 #define DISP_DITHER_SIZE                       0x0030

 #define LUT_10BIT_MASK                         0x03ff
@@ -166,6 +167,8 @@ void mtk_dither_set_common(void __iomem *regs,
struct cmdq_client_reg *cmdq_reg,
                              DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
                              cmdq_reg, regs, DISP_DITHER_16);
                mtk_ddp_write(cmdq_pkt, dither_en, cmdq_reg, regs, cfg);
+       } else {
+               mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, cmdq_reg, regs, cfg);
        }
 }

@@ -315,8 +318,12 @@ static void mtk_dither_config(struct device *dev,
unsigned int w,
 {
        struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);

-       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg,
priv->regs, DISP_DITHER_SIZE);
-       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
priv->regs, DISP_DITHER_CFG);
+       mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+                     DISP_DITHER_SIZE);
+       mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs,
+                     DISP_DITHER_CFG);
+       mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc, DISP_DITHER_CFG,
+                              DITHER_ENGINE_EN, cmdq_pkt);
 }

So now, not only bpc==5 or 6, but all valid bpc, dither config will
call mtk_dither_set_common() with the flag DITHER_ENGINE_EN(BIT(1)).
od config will call mtk_dither_set_common() with the flag
DISP_DITHERING(BIT(2)).
Additionally for 8173, gamma config will call mtk_dither_set_common()
with the flag DISP_DITHERING (BIT(2))

For invalid mode all of them will be DITHER_RELAY_MODE.

Just to make sure that this follows the spec? thanks

> >
> > -     mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs, DISP_DITHER_SIZE);
> > -     mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg, priv->regs, DISP_DITHER_CFG);
> > +     if (enable) {
> > +             mtk_dither_set_common(priv->regs, &priv->cmdq_reg, bpc,
> > +                                   DISP_DITHER_CFG, DITHER_ENGINE_EN,
> > +                                   cmdq_pkt);
> > +     } else {
> > +             mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, &priv->cmdq_reg,
> > +                           priv->regs, DISP_DITHER_CFG);
> > +     }
> > +
> > +     mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
> > +                   DISP_DITHER_SIZE);
> >  }
> >
> >  static void mtk_dither_start(struct device *dev)
>
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  reply	other threads:[~2021-01-29  8:12 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-28 11:23 [PATCH v12 0/8] drm/mediatek: add support for mediatek SOC MT8183 Hsin-Yi Wang
2021-01-28 11:23 ` [PATCH v12 1/8] arm64: dts: mt8183: rename rdma fifo size Hsin-Yi Wang
2021-01-28 16:31   ` Matthias Brugger
2021-01-28 11:23 ` [PATCH v12 2/8] arm64: dts: mt8183: refine gamma compatible name Hsin-Yi Wang
2021-01-28 16:33   ` Matthias Brugger
2021-01-28 11:23 ` [PATCH v12 3/8] drm/mediatek: add mtk_dither_set_common() function Hsin-Yi Wang
2021-01-28 11:23 ` [PATCH v12 4/8] drm/mediatek: separate gamma module Hsin-Yi Wang
2021-01-28 11:23 ` [PATCH v12 5/8] drm/mediatek: add has_dither private data for gamma Hsin-Yi Wang
2021-01-28 11:23 ` [PATCH v12 6/8] drm/mediatek: enable dither function Hsin-Yi Wang
2021-01-29  1:33   ` CK Hu
2021-01-29  6:24     ` Hsin-Yi Wang [this message]
2021-01-29  6:30       ` Yongqiang Niu
2021-01-29  6:46         ` Hsin-Yi Wang
2021-01-29  7:42           ` Yongqiang Niu
2021-01-29  7:59             ` Hsin-Yi Wang
2021-01-28 11:23 ` [PATCH v12 7/8] soc: mediatek: add mtk mutex support for MT8183 Hsin-Yi Wang
2021-01-29  1:11   ` CK Hu
2021-01-28 11:23 ` [PATCH v12 8/8] drm/mediatek: add support for mediatek SOC MT8183 Hsin-Yi Wang

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