From: Jagan Teki <jagan@amarulasolutions.com>
To: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Chen-Yu Tsai <wens@csie.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
dri-devel <dri-devel@lists.freedesktop.org>,
devicetree <devicetree@vger.kernel.org>,
Michael Trimarchi <michael@amarulasolutions.com>,
linux-amarula@amarulasolutions.com,
linux-sunxi <linux-sunxi@googlegroups.com>
Subject: Re: [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes
Date: Mon, 11 Mar 2019 21:36:27 +0530 [thread overview]
Message-ID: <CAMty3ZChz=s7gdQyX9KnsAp1t5FrpouXGK74-r0SKJ89yJN67Q@mail.gmail.com> (raw)
In-Reply-To: <20190311153847.oz6ruqmptaq2befn@flea>
On Mon, Mar 11, 2019 at 9:08 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Mon, Mar 11, 2019 at 07:06:24PM +0530, Jagan Teki wrote:
> > pll-video => pll-mipi => tcon0 => tcon0-pixel-clock is the typical
> > MIPI clock topology in Allwinner DSI controller.
> >
> > TCON dotclock driver is computing the desired DCLK divider based on
> > panel pixel clock along with input DCLK min, max divider values from
> > tcon driver and that would eventually set the pll-mipi clock rate.
> >
> > The current code allows the TCON clock divider to have a default 4
> > for min, max ranges that would fail to compute the desired pll-mipi
> > rate while supporting new panels.
> >
> > So, add the computation logic 'format/lanes' to dclk min and max dividers
> > and instead of default 4. This computation logic align with Allwinner A64
> > BSP, hoping that would work even for A33.
>
> Last time we discussed this, we found out that this wasn't the case,
> even in the BSP.
This was the case for BSP to compute pll-mipi not for TCON_DSI clock
register, SUN4I_TCON0_DCLK_REG, which marked the divider 4 by default.
>
> What compelling evidence have you found that makes you say otherwise?
divider 4 isn't worked, this I would mentioned before as well.
Tested this on 4 different panels, and below are the desired divider values
and pll-mipi clock rate with respect to pixel clock frequency.
- 55MHz pixel clock with 4-lane panel, and the desired DSI clock divider
is 6 with the output parent clock rate of 330MHz.
- 30MHz pixel clock with 4-lane panel, and the desired DSI clock divider
is 6 with parent clock rate of 180MHz.
- 27.5Mhz pixel clock with 2-lane pane, and the desired DSI clock divider
is 12 with the output parent clock rate of 330MHz.
- 147MHz pixel clock with 4-lane panel, and the desired DSI clock divider
is 6 with the output parent clock rate of 882MHz.
BSP trying to use this format/lane to compute dsi divider that in-turn
using pll-mipi set_rate but TCON0_DCLK_REG keep constant 4.
next prev parent reply other threads:[~2019-03-11 16:06 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-11 13:36 [PATCH v8 00/15] drm/sun4i: Allwinner A64 MIPI-DSI support Jagan Teki
2019-03-11 13:36 ` [PATCH v8 01/15] drm/sun4i: dsi: Fix video start delay computation Jagan Teki
[not found] ` <20190311133637.18334-2-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2019-03-11 15:37 ` Maxime Ripard
2019-03-11 16:01 ` Jagan Teki
[not found] ` <CAMty3ZDDARP02qMJZ9CXeiMv=kghoiUHgEAV9b4q+SrbLss40Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-03-19 10:25 ` Maxime Ripard
2019-03-21 14:38 ` Jagan Teki
2019-04-02 13:34 ` Jagan Teki
[not found] ` <CAMty3ZC+dTVuc2TWR=cqKNbrZe6j2vnwfXAqg6RbvduvY_63LA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-04-02 14:45 ` Maxime Ripard
2019-03-11 13:36 ` [PATCH v8 04/15] drm/sun4i: dsi: Probe tcon0 during dsi_bind Jagan Teki
[not found] ` <20190311133637.18334-1-jagan-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/@public.gmane.org>
2019-03-11 13:36 ` [PATCH v8 02/15] drm/sun4i: tcon: Compute DCLK dividers based on format, lanes Jagan Teki
2019-03-11 15:38 ` Maxime Ripard
2019-03-11 16:06 ` Jagan Teki [this message]
2019-03-18 18:24 ` Jagan Teki
[not found] ` <CAMty3ZChz=s7gdQyX9KnsAp1t5FrpouXGK74-r0SKJ89yJN67Q-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-03-19 10:53 ` Maxime Ripard
2019-03-19 12:17 ` Sergey Suloev
[not found] ` <7dab458e-7fad-2dbe-bbae-bd3cdf89dcb4-RHPENKW2UW+1Z/+hSey0Gg@public.gmane.org>
2019-03-21 14:11 ` Jagan Teki
2019-03-21 14:10 ` Jagan Teki
[not found] ` <CAMty3ZCjTLLw+zAfPKD3qZx_o9yti4MD0XL0Ve7VG1_6ToJ=pg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-04-02 13:33 ` Jagan Teki
2019-04-02 14:39 ` Maxime Ripard
2019-03-11 13:36 ` [PATCH v8 03/15] drm/sun4i: tcon: Export get tcon0 routine Jagan Teki
2019-03-11 13:36 ` [PATCH v8 05/15] drm/sun4i: dsi: Get tcon0_div at runtime Jagan Teki
2019-03-11 13:36 ` [PATCH v8 06/15] dt-bindings: sun6i-dsi: Add VCC-DSI supply property Jagan Teki
2019-03-11 13:36 ` [PATCH v8 08/15] dt-bindings: sun6i-dsi: Add A64 DPHY compatible (w/ A31 fallback) Jagan Teki
2019-03-11 13:36 ` [PATCH v8 09/15] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk Jagan Teki
2019-03-11 13:36 ` [PATCH v8 12/15] arm64: dts: allwinner: a64: Add MIPI DSI pipeline Jagan Teki
2019-03-11 13:36 ` [DO NOT MERGE] [PATCH v8 15/15] arm64: dts: allwinner: bananapi-m64: Enable Bananapi S070WV20-CT16 DSI panel Jagan Teki
2019-03-11 13:36 ` [PATCH v8 07/15] dt-bindings: sun6i-dsi: Add A64 MIPI-DSI compatible Jagan Teki
2019-03-11 13:36 ` [PATCH v8 10/15] drm/sun4i: sun6i_mipi_dsi: Add has_mod_clk quirk Jagan Teki
2019-03-11 13:36 ` [PATCH v8 11/15] drm/sun4i: sun6i_mipi_dsi: Add Allwinner A64 MIPI DSI support Jagan Teki
2019-03-11 13:36 ` [PATCH v8 13/15] arm64: dts: allwinner: a64-amarula-relic: Add Techstar TS8550B MIPI-DSI panel Jagan Teki
2019-03-11 13:36 ` [DO NOT MERGE] [PATCH v8 14/15] arm64: dts: allwinner: a64-pine64-lts: Enable Feiyang FY07024DI26A30-D DSI panel Jagan Teki
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