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Wed, 15 Apr 2020 14:08:06 +0000 Received: from MN2PR12MB4488.namprd12.prod.outlook.com ([fe80::5868:c9cf:2687:6e03]) by MN2PR12MB4488.namprd12.prod.outlook.com ([fe80::5868:c9cf:2687:6e03%2]) with mapi id 15.20.2900.028; Wed, 15 Apr 2020 14:08:06 +0000 From: "Deucher, Alexander" To: "Koenig, Christian" , Jani Nikula , Alex Deucher , Bernard Zhao Subject: Re: [PATCH] Optimized division operation to shift operation Thread-Topic: [PATCH] Optimized division operation to shift operation Thread-Index: AQHWElDOphctbVDwzky6oxRY89/LXqh47JqAgADhWoCAAARfAIAAZ4LW Date: Wed, 15 Apr 2020 14:08:06 +0000 Message-ID: References: <1586864113-30682-1-git-send-email-bernard@vivo.com> <87lfmx5h72.fsf@intel.com>, In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_Enabled=True; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_SetDate=2020-04-15T14:08:05.440Z; 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boundary="===============0316639365==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============0316639365== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB448868370D02A066FACA9955F7DB0MN2PR12MB4488namp_" --_000_MN2PR12MB448868370D02A066FACA9955F7DB0MN2PR12MB4488namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] I've gone ahead and dropped the patch. Alex ________________________________ From: Koenig, Christian Sent: Wednesday, April 15, 2020 3:57 AM To: Jani Nikula ; Alex Deucher ; Bernard Zhao Cc: Sierra Guiza, Alejandro (Alex) ; Zeng, Oak ; Maling list - DRI developers = ; David Airlie ; Kuehling, Felix = ; LKML ; amd-gfx list ; kernel@vivo.com ; Huang, Ray = ; Russell, Kent ; Deucher, Alexander ; Sam Ravnborg ; Yuan, Xiaojie Subject: Re: [PATCH] Optimized division operation to shift operation Am 15.04.20 um 09:41 schrieb Jani Nikula: > On Tue, 14 Apr 2020, Alex Deucher wrote: >> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao wrote: >>> On some processors, the / operate will call the compiler`s div lib, >>> which is low efficient, We can replace the / operation with shift, >>> so that we can replace the call of the division library with one >>> shift assembly instruction. > This was applied already, and it's not in a driver I look after... but > to me this feels like something that really should be > justified. Using >> instead of / for multiples of 2 division mattered 20 > years ago, I'd be surprised if it still did on modern compilers. I have similar worries, especially since we replace the "/ (4 * 2)" with ">> 3" it's making the code just a bit less readable. And that the code runs exactly once while loading the driver and pushing the firmware into the hardware. So performance is completely irrelevant here. Regards, Christian. > > BR, > Jani. > > >>> Signed-off-by: Bernard Zhao >> Applied. thanks. >> >> Alex >> >>> --- >>> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- >>> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- >>> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- >>> 3 files changed, 6 insertions(+), 6 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/am= d/amdgpu/gmc_v6_0.c >>> index b205039..66cd078 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c >>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcode(struct amdg= pu_device *adev) >>> amdgpu_ucode_print_mc_hdr(&hdr->header); >>> >>> adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version= ); >>> - regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); >>> + regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3; >>> new_io_mc_regs =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_= offset_bytes)); >>> - ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4; >>> + ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; >>> new_fw_data =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_ar= ray_offset_bytes)); >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/am= d/amdgpu/gmc_v7_0.c >>> index 9da9596..ca26d63 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c >>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcode(struct amdg= pu_device *adev) >>> amdgpu_ucode_print_mc_hdr(&hdr->header); >>> >>> adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version= ); >>> - regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); >>> + regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3; >>> io_mc_regs =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_= offset_bytes)); >>> - ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4; >>> + ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; >>> fw_data =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_ar= ray_offset_bytes)); >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/am= d/amdgpu/gmc_v8_0.c >>> index 27d83204..295039c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c >>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_microcode(struc= t amdgpu_device *adev) >>> amdgpu_ucode_print_mc_hdr(&hdr->header); >>> >>> adev->gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version= ); >>> - regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2); >>> + regs_size =3D le32_to_cpu(hdr->io_debug_size_bytes) >> 3; >>> io_mc_regs =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_= offset_bytes)); >>> - ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) / 4; >>> + ucode_size =3D le32_to_cpu(hdr->header.ucode_size_bytes) >> 2; >>> fw_data =3D (const __le32 *) >>> (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_ar= ray_offset_bytes)); >>> >>> -- >>> 2.7.4 >>> >>> _______________________________________________ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flis= ts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D02%7C01%7Cchri= stian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e6= 08e11a82d994e183d%7C0%7C0%7C637225333103893889&sdata=3DVDJlEY2%2Bl1SSO8= Fw1dYqqPFqQtyHpsxQ0Tm7iVOgJQY%3D&reserved=3D0 >> _______________________________________________ >> dri-devel mailing list >> dri-devel@lists.freedesktop.org >> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flist= s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-devel&data=3D02%7C01%7Cchr= istian.koenig%40amd.com%7C1e91f7edcfe0473b0d7008d7e11074a8%7C3dd8961fe4884e= 608e11a82d994e183d%7C0%7C0%7C637225333103893889&sdata=3DEpqRRbCiksur%2B= jMlVQplExuJsmw6UPODhyBOutOVukw%3D&reserved=3D0 --_000_MN2PR12MB448868370D02A066FACA9955F7DB0MN2PR12MB4488namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Public Use]


I've gone ahead and dropped the patch.

Alex
From: Koenig, Christian <= ;Christian.Koenig@amd.com>
Sent: Wednesday, April 15, 2020 3:57 AM
To: Jani Nikula <jani.nikula@linux.intel.com>; Alex Deucher &l= t;alexdeucher@gmail.com>; Bernard Zhao <bernard@vivo.com>
Cc: Sierra Guiza, Alejandro (Alex) <Alex.Sierra@amd.com>; Zeng= , Oak <Oak.Zeng@amd.com>; Maling list - DRI developers <dri-devel@= lists.freedesktop.org>; David Airlie <airlied@linux.ie>; Kuehling,= Felix <Felix.Kuehling@amd.com>; LKML <linux-kernel@vger.kernel.or= g>; amd-gfx list <amd-gfx@lists.freedesktop.org>; kernel@vivo.com <ke= rnel@vivo.com>; Huang, Ray <Ray.Huang@amd.com>; Russell, Kent <= Kent.Russell@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com&= gt;; Sam Ravnborg <sam@ravnborg.org>; Yuan, Xiaojie <Xiaojie.Yuan@= amd.com>
Subject: Re: [PATCH] Optimized division operation to shift operation=
 
Am 15.04.20 um 09:41 schrieb Jani Nikula:
> On Tue, 14 Apr 2020, Alex Deucher <alexdeucher@gmail.com> wrote:=
>> On Tue, Apr 14, 2020 at 9:05 AM Bernard Zhao <bernard@vivo.com&= gt; wrote:
>>> On some processors, the / operate will call the compiler`s div= lib,
>>> which is low efficient, We can replace the / operation with sh= ift,
>>> so that we can replace the call of the division library with o= ne
>>> shift assembly instruction.
> This was applied already, and it's not in a driver I look after... but=
> to me this feels like something that really should be
> justified. Using >> instead of / for multiples of 2 division mat= tered 20
> years ago, I'd be surprised if it still did on modern compilers.

I have similar worries, especially since we replace the "/ (4 * 2)&quo= t; with
">> 3" it's making the code just a bit less readable.

And that the code runs exactly once while loading the driver and pushing the firmware into the hardware. So performance is completely irrelevant here.

Regards,
Christian.

>
> BR,
> Jani.
>
>
>>> Signed-off-by: Bernard Zhao <bernard@vivo.com>
>> Applied.  thanks.
>>
>> Alex
>>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 += 3;--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 += 3;--
>>>   drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 += 3;--
>>>   3 files changed, 6 insertions(+), 6 deletions(= -)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/g= pu/drm/amd/amdgpu/gmc_v6_0.c
>>> index b205039..66cd078 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
>>> @@ -175,10 +175,10 @@ static int gmc_v6_0_mc_load_microcod= e(struct amdgpu_device *adev)
>>>          amdgpu_u= code_print_mc_hdr(&hdr->header);
>>>
>>>          adev->= ;gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size =3D le32_to_cp= u(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size =3D le32_t= o_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          new_io_m= c_regs =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size =3D le32_to_c= pu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size =3D le32_= to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          new_fw_d= ata =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/g= pu/drm/amd/amdgpu/gmc_v7_0.c
>>> index 9da9596..ca26d63 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
>>> @@ -193,10 +193,10 @@ static int gmc_v7_0_mc_load_microcod= e(struct amdgpu_device *adev)
>>>          amdgpu_u= code_print_mc_hdr(&hdr->header);
>>>
>>>          adev->= ;gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size =3D le32_to_cp= u(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size =3D le32_t= o_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_re= gs =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size =3D le32_to_c= pu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size =3D le32_= to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/g= pu/drm/amd/amdgpu/gmc_v8_0.c
>>> index 27d83204..295039c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
>>> @@ -318,10 +318,10 @@ static int gmc_v8_0_tonga_mc_load_mi= crocode(struct amdgpu_device *adev)
>>>          amdgpu_u= code_print_mc_hdr(&hdr->header);
>>>
>>>          adev->= ;gmc.fw_version =3D le32_to_cpu(hdr->header.ucode_version);
>>> -       regs_size =3D le32_to_cp= u(hdr->io_debug_size_bytes) / (4 * 2);
>>> +       regs_size =3D le32_t= o_cpu(hdr->io_debug_size_bytes) >> 3;
>>>          io_mc_re= gs =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->io_debug_array_offset_bytes));
>>> -       ucode_size =3D le32_to_c= pu(hdr->header.ucode_size_bytes) / 4;
>>> +       ucode_size =3D le32_= to_cpu(hdr->header.ucode_size_bytes) >> 2;
>>>          fw_data = =3D (const __le32 *)
>>>          &nb= sp;       (adev->gmc.fw->data + le3= 2_to_cpu(hdr->header.ucode_array_offset_bytes));
>>>
>>> --
>>> 2.7.4
>>>
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