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boundary="===============1412815911==" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --===============1412815911== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB4488DFD306A90EE9F1F44F9BF7B29MN2PR12MB4488namp_" --_000_MN2PR12MB4488DFD306A90EE9F1F44F9BF7B29MN2PR12MB4488namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - Internal Distribution Only] Good question. I think push it to drm-misc-next for upstream. We can carr= y it internally in amd-staging-drm-next for internal testing and I can coor= dinate with drm-next. I think the amdgpu changes are pretty straightforwar= d, so shouldn't be too hard keep the merge straight. I dunno. Alex ________________________________ From: Christian K=F6nig Sent: Friday, February 5, 2021 4:58 AM To: Liu, Leo ; amd-gfx@lists.freedesktop.org ; dri-devel@lists.freedesktop.org ; Deucher, Alexander Subject: Re: [PATCH 3/3] drm/amdgpu: share scheduler score on VCN3 instance= s Alex how do we want to merge this? I've just pushed the first patch to drm-misc-next since that needed a rebase because it touches other drivers as well. But the rest is really AMD specific and I'm not sure if the dependent stuff is already in there as well. So if I push it to drm-misc-next you will probably need to merge and if I push it to amd-staging-drm-next somebody else might need to merge when drm-misc-next is merged. Ideas? Christian. Am 04.02.21 um 19:34 schrieb Leo Liu: > The series are: > > Reviewed-and-Tested-by: Leo Liu > > > On 2021-02-04 9:44 a.m., Christian K=F6nig wrote: >> The VCN3 instances can do both decode as well as encode. >> >> Share the scheduler load balancing score and remove fixing encode to >> only the second instance. >> >> Signed-off-by: Christian K=F6nig >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 + >> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 11 +++++++---- >> 2 files changed, 8 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h >> index 13aa417f6be7..d10bc4f0a05f 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h >> @@ -211,6 +211,7 @@ struct amdgpu_vcn_inst { >> void *saved_bo; >> struct amdgpu_ring ring_dec; >> struct amdgpu_ring ring_enc[AMDGPU_VCN_MAX_ENC_RINGS]; >> + atomic_t sched_score; >> struct amdgpu_irq_src irq; >> struct amdgpu_vcn_reg external; >> struct amdgpu_bo *dpg_sram_bo; >> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> index 239a4eb52c61..b33f513fd2ac 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c >> @@ -171,6 +171,7 @@ static int vcn_v3_0_sw_init(void *handle) >> for (i =3D 0; i < adev->vcn.num_vcn_inst; i++) { >> volatile struct amdgpu_fw_shared *fw_shared; >> + >> if (adev->vcn.harvest_config & (1 << i)) >> continue; >> @@ -198,6 +199,8 @@ static int vcn_v3_0_sw_init(void *handle) >> if (r) >> return r; >> + atomic_set(&adev->vcn.inst[i].sched_score, 0); >> + >> ring =3D &adev->vcn.inst[i].ring_dec; >> ring->use_doorbell =3D true; >> if (amdgpu_sriov_vf(adev)) { >> @@ -209,7 +212,8 @@ static int vcn_v3_0_sw_init(void *handle) >> ring->no_scheduler =3D true; >> sprintf(ring->name, "vcn_dec_%d", i); >> r =3D amdgpu_ring_init(adev, ring, 512, >> &adev->vcn.inst[i].irq, 0, >> - AMDGPU_RING_PRIO_DEFAULT, NULL); >> + AMDGPU_RING_PRIO_DEFAULT, >> + &adev->vcn.inst[i].sched_score); >> if (r) >> return r; >> @@ -227,11 +231,10 @@ static int vcn_v3_0_sw_init(void *handle) >> } else { >> ring->doorbell_index =3D >> (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 * i; >> } >> - if (adev->asic_type =3D=3D CHIP_SIENNA_CICHLID && i !=3D 1) >> - ring->no_scheduler =3D true; >> sprintf(ring->name, "vcn_enc_%d.%d", i, j); >> r =3D amdgpu_ring_init(adev, ring, 512, >> &adev->vcn.inst[i].irq, 0, >> - AMDGPU_RING_PRIO_DEFAULT, NULL); >> + AMDGPU_RING_PRIO_DEFAULT, >> + &adev->vcn.inst[i].sched_score); >> if (r) >> return r; >> } --_000_MN2PR12MB4488DFD306A90EE9F1F44F9BF7B29MN2PR12MB4488namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - Internal Distribution Only]


Good question.  I think push it to drm-misc-next for upstream.  W= e can carry it internally in amd-staging-drm-next for internal testing and = I can coordinate with drm-next.  I think the amdgpu changes are pretty= straightforward, so shouldn't be too hard keep the merge straight.  I dunno. 

Alex

From: Christian K=F6nig <= ;ckoenig.leichtzumerken@gmail.com>
Sent: Friday, February 5, 2021 4:58 AM
To: Liu, Leo <Leo.Liu@amd.com>; amd-gfx@lists.freedesktop.org = <amd-gfx@lists.freedesktop.org>; dri-devel@lists.freedesktop.org <= dri-devel@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deuch= er@amd.com>
Subject: Re: [PATCH 3/3] drm/amdgpu: share scheduler score on VCN3 i= nstances
 
Alex how do we want to merge this?

I've just pushed the first patch to drm-misc-next since that needed a
rebase because it touches other drivers as well.

But the rest is really AMD specific and I'm not sure if the dependent
stuff is already in there as well.

So if I push it to drm-misc-next you will probably need to merge and if I push it to amd-staging-drm-next somebody else might need to merge when drm-misc-next is merged.

Ideas?

Christian.

Am 04.02.21 um 19:34 schrieb Leo Liu:
> The series are:
>
> Reviewed-and-Tested-by: Leo Liu <leo.liu@amd.com>
>
>
> On 2021-02-04 9:44 a.m., Christian K=F6nig wrote:
>> The VCN3 instances can do both decode as well as encode.
>>
>> Share the scheduler load balancing score and remove fixing encode = to
>> only the second instance.
>>
>> Signed-off-by: Christian K=F6nig <christian.koenig@amd.com><= br> >> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  1 +
>>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 11 ++++= +++----
>>   2 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index 13aa417f6be7..d10bc4f0a05f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -211,6 +211,7 @@ struct amdgpu_vcn_inst {
>>       void     &= nbsp;      *saved_bo;
>>       struct amdgpu_ring   = ; ring_dec;
>>       struct amdgpu_ring   = ; ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
>> +    atomic_t      &n= bsp; sched_score;
>>       struct amdgpu_irq_src  &n= bsp; irq;
>>       struct amdgpu_vcn_reg  &n= bsp; external;
>>       struct amdgpu_bo    = *dpg_sram_bo;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> index 239a4eb52c61..b33f513fd2ac 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
>> @@ -171,6 +171,7 @@ static int vcn_v3_0_sw_init(void *handle)
>>         for (i =3D 0; i < adev-&g= t;vcn.num_vcn_inst; i++) {
>>           volatile st= ruct amdgpu_fw_shared *fw_shared;
>> +
>>           if (adev-&g= t;vcn.harvest_config & (1 << i))
>>            =    continue;
>>   @@ -198,6 +199,8 @@ static int vcn_v3_0_sw_init(void *handl= e)
>>           if (r)
>>            =    return r;
>>   +        atomic_set(&= ;adev->vcn.inst[i].sched_score, 0);
>> +
>>           ring =3D &a= mp;adev->vcn.inst[i].ring_dec;
>>           ring->us= e_doorbell =3D true;
>>           if (amdgpu_= sriov_vf(adev)) {
>> @@ -209,7 +212,8 @@ static int vcn_v3_0_sw_init(void *handle)
>>            =    ring->no_scheduler =3D true;
>>           sprintf(rin= g->name, "vcn_dec_%d", i);
>>           r =3D amdgp= u_ring_init(adev, ring, 512,
>> &adev->vcn.inst[i].irq, 0,
>> -           = ;          AMDGPU_RING_PRIO_DE= FAULT, NULL);
>> +           = ;          AMDGPU_RING_PRIO_DE= FAULT,
>> +           = ;          &adev->vcn.i= nst[i].sched_score);
>>           if (r)
>>            =    return r;
>>   @@ -227,11 +231,10 @@ static int vcn_v3_0_sw_init(void *han= dle)
>>            =    } else {
>>            =        ring->doorbell_index =3D
>> (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 2 + j + 8 *= i;
>>            =    }
>> -           = ; if (adev->asic_type =3D=3D CHIP_SIENNA_CICHLID && i !=3D 1) >> -           = ;     ring->no_scheduler =3D true;
>>            =    sprintf(ring->name, "vcn_enc_%d.%d", i, j);
>>            =    r =3D amdgpu_ring_init(adev, ring, 512,
>> &adev->vcn.inst[i].irq, 0,
>> -           = ;            &n= bsp; AMDGPU_RING_PRIO_DEFAULT, NULL);
>> +           = ;            &n= bsp; AMDGPU_RING_PRIO_DEFAULT,
>> + &adev->vcn.inst[i].sched_score);
>>            =    if (r)
>>            =        return r;
>>           }

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