From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor
Date: Tue, 1 Jun 2021 16:20:05 -0400 [thread overview]
Message-ID: <YLaWdU2mLu/Ih2Yp@intel.com> (raw)
In-Reply-To: <20210525054803.7387-5-daniele.ceraolospurio@intel.com>
On Mon, May 24, 2021 at 10:47:50PM -0700, Daniele Ceraolo Spurio wrote:
> From: Chris Wilson <chris@chris-wilson.co.uk>
>
> Allow internal clients to create a pinned context.
>
> v2 (Daniele): export destructor as well, allow optional usage of custom
> vm for maximum flexibility.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_engine.h | 10 ++++++++
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 29 +++++++++++++++--------
> 2 files changed, 29 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index 47ee8578e511..a64d28aba257 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -18,7 +18,9 @@
> #include "intel_workarounds.h"
>
> struct drm_printer;
> +struct intel_context;
> struct intel_gt;
> +struct lock_class_key;
>
> /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
> * but keeps the logic simple. Indeed, the whole purpose of this macro is just
> @@ -255,6 +257,14 @@ struct i915_request *
> intel_engine_find_active_request(struct intel_engine_cs *engine);
>
> u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> + struct i915_address_space *vm,
> + unsigned int ring_size,
> + unsigned int hwsp,
> + struct lock_class_key *key,
> + const char *name);
> +void intel_engine_destroy_pinned_context(struct intel_context *ce);
>
> void intel_engine_init_active(struct intel_engine_cs *engine,
> unsigned int subclass);
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index eba2da9679a5..8cbf11497e8e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -801,11 +801,13 @@ intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
> #endif
> }
>
> -static struct intel_context *
> -create_pinned_context(struct intel_engine_cs *engine,
> - unsigned int hwsp,
> - struct lock_class_key *key,
> - const char *name)
> +struct intel_context *
> +intel_engine_create_pinned_context(struct intel_engine_cs *engine,
> + struct i915_address_space *vm,
> + unsigned int ring_size,
> + unsigned int hwsp,
> + struct lock_class_key *key,
> + const char *name)
> {
> struct intel_context *ce;
> int err;
> @@ -816,6 +818,12 @@ create_pinned_context(struct intel_engine_cs *engine,
>
> __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
> ce->timeline = page_pack_bits(NULL, hwsp);
> + ce->ring = __intel_context_ring_size(ring_size);
why do we need this now and we didn't need before?
> +
> + if (vm) {
> + i915_vm_put(ce->vm);
> + ce->vm = i915_vm_get(vm);
> + }
same question here...
>
> err = intel_context_pin(ce); /* perma-pin so it is always available */
> if (err) {
> @@ -834,7 +842,7 @@ create_pinned_context(struct intel_engine_cs *engine,
> return ce;
> }
>
> -static void destroy_pinned_context(struct intel_context *ce)
> +void intel_engine_destroy_pinned_context(struct intel_context *ce)
> {
> struct intel_engine_cs *engine = ce->engine;
> struct i915_vma *hwsp = engine->status_page.vma;
> @@ -854,8 +862,9 @@ create_kernel_context(struct intel_engine_cs *engine)
> {
> static struct lock_class_key kernel;
>
> - return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
> - &kernel, "kernel_context");
> + return intel_engine_create_pinned_context(engine, NULL, SZ_4K,
> + I915_GEM_HWS_SEQNO_ADDR,
> + &kernel, "kernel_context");
> }
>
> /**
> @@ -898,7 +907,7 @@ static int engine_init_common(struct intel_engine_cs *engine)
> return 0;
>
> err_context:
> - destroy_pinned_context(ce);
> + intel_engine_destroy_pinned_context(ce);
> return ret;
> }
>
> @@ -956,7 +965,7 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
> fput(engine->default_state);
>
> if (engine->kernel_context)
> - destroy_pinned_context(engine->kernel_context);
> + intel_engine_destroy_pinned_context(engine->kernel_context);
>
> GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
> cleanup_status_page(engine);
> --
> 2.29.2
>
next prev parent reply other threads:[~2021-06-01 20:20 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-25 5:47 [PATCH v4 00/17] drm/i915: Introduce Intel PXP Daniele Ceraolo Spurio
2021-05-25 5:47 ` [PATCH v4 01/17] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio
2021-05-25 5:47 ` [PATCH v4 02/17] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio
2021-06-02 19:10 ` Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 03/17] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio
2021-05-25 5:47 ` [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor Daniele Ceraolo Spurio
2021-06-01 20:20 ` Rodrigo Vivi [this message]
2021-06-01 21:23 ` Daniele Ceraolo Spurio
2021-06-02 18:18 ` Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 05/17] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio
2021-06-01 20:24 ` [Intel-gfx] " Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 06/17] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio
2021-06-01 20:26 ` Rodrigo Vivi
2021-06-03 0:07 ` [Intel-gfx] " Teres Alexis, Alan Previn
2021-05-25 5:47 ` [PATCH v4 07/17] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio
2021-05-25 5:47 ` [PATCH v4 08/17] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio
2021-06-01 20:32 ` Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 09/17] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio
2021-05-25 20:24 ` kernel test robot
2021-05-25 5:47 ` [PATCH v4 10/17] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio
2021-06-02 16:06 ` [Intel-gfx] " Rodrigo Vivi
2021-06-02 16:08 ` Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 11/17] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio
2021-05-27 10:10 ` [Intel-gfx] " Daniel Vetter
2021-05-25 5:47 ` [PATCH v4 12/17] drm/i915/pxp: start the arb session on demand Daniele Ceraolo Spurio
2021-06-02 18:14 ` [Intel-gfx] " Rodrigo Vivi
2021-06-10 22:44 ` Daniele Ceraolo Spurio
2021-06-11 8:38 ` Rodrigo Vivi
2021-05-25 5:47 ` [PATCH v4 13/17] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio
2021-06-02 16:20 ` Rodrigo Vivi
2021-06-10 22:58 ` Daniele Ceraolo Spurio
2021-06-11 8:44 ` Rodrigo Vivi
2021-05-25 5:48 ` [PATCH v4 14/17] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio
2021-05-25 13:32 ` Daniel Vetter
2021-05-27 2:03 ` Daniele Ceraolo Spurio
2021-05-25 18:36 ` [Intel-gfx] " Tang, CQ
2021-05-27 2:13 ` Daniele Ceraolo Spurio
2021-05-25 5:48 ` [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio
2021-06-02 18:23 ` Rodrigo Vivi
2021-05-25 5:48 ` [PATCH v4 16/17] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio
2021-06-02 19:00 ` Rodrigo Vivi
2021-05-25 5:48 ` [PATCH v4 17/17] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YLaWdU2mLu/Ih2Yp@intel.com \
--to=rodrigo.vivi@intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=daniele.ceraolospurio@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).