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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?i8wu2tyhzfXY46MMP+6o0bjRZCvzULpXoT3AD9m3oFXfkJm+tL8g1xKwN9ir?= =?us-ascii?Q?n07omtne6N1VLF+GOxPSaiTsqSb+uwBhvvMjvEoZjwlKfEb8kUCsiL329CU+?= =?us-ascii?Q?jrizRve7/9OUMxQJBrR4TpJG23nAV47h3TMKZ4jey9jgGZkzJq/CAMMRetUb?= =?us-ascii?Q?sfPJCOsLjv1Oe8KcItoeajcftHDEoqsXFLomu6OnKjRYp3F16msn8HlilsLj?= =?us-ascii?Q?fRWUSv0nslgsi1VigKe5X0UPThykdD6nAeH8Sqlq8p3qamwzR2v+6tKLn1wi?= =?us-ascii?Q?3SLiYYsB0nrKvUk6Hs3bOXN57M0mIdX1uH7vWbZ6HYWpURCOFB5VjvQjxhK3?= =?us-ascii?Q?Rlt5dMCVR/k8QN95nCfmCSGhQ4wus/HxjQQYZBtU8z0gHA7EGdVUZfA9OrJ5?= =?us-ascii?Q?1WyLx9DLxDqBj+WWZb54xJLoPA0NECHt4ER0DneCnAx5iNkOcAaEsSZrQPer?= =?us-ascii?Q?RO3YvPMzqQuKnEv5OGi3+iq7B2BNYJAHp1KkhEOhqGPk9Iw0ymPi1SSpBYSs?= =?us-ascii?Q?21qJx6d7upAQHrjzGM6PM2Od7jnQasoy6lDZlgUBEAGpxEOBmEO5T9QHJYMf?= =?us-ascii?Q?9P28YHRI0zWaDCliSCoWOiuag4QYkGPZbqWf7tep3ZZDSlaLPDS7FqnTh6/I?= =?us-ascii?Q?mIiZOBkkMEol/Rgqug7WK8LV3xfdLTqmpoD+ii84sTl6YFC22h5apcQa14j8?= =?us-ascii?Q?rVfqFMqRu1HI4fKdvx92jDFw+dgNIIiHWB+LSgn4M2xjzqJxwtBEQD+M0sQh?= =?us-ascii?Q?bkITegsPuRQfrDcqtWpV1eaMSbUN5Ql2UBAqoJdiE9mILO3MFCh7y+0plATB?= =?us-ascii?Q?sY95x2yr1ArEKRfzxMpbMBUt4TxsMC9Aa9eM9YyxIAKXQ5PEBsHVCaM2AzjE?= =?us-ascii?Q?va4t22GbsT+hAY4pE/MXP5+AOP25yeEGtbwr7sDfE9Sm3Ff/pVnVydADL7SW?= =?us-ascii?Q?KZVD3OgCrud5Mppnv0a6VEzXE59r6DsoTgOd2SeFCMty6SdB6bvYp8A6CVng?= =?us-ascii?Q?SVqtwnGH5q/6ap4Z02EJ5c5ZNX/vScQJgN7f6dU6813gI2PYz14RUhy8j1/J?= =?us-ascii?Q?6ddJaFi7W+mJLTZ34u/c/Iy9cCBoG45TceRXWkkGpnL/jc39RNLDxAD4CqXa?= =?us-ascii?Q?xeNIw7fUuDETW38hATI9WvzoHeV5ihvgxUkKGNWyS+YOm038SOVt7sa+xdmK?= =?us-ascii?Q?4Z0hAPar5LebudmU4a9ujZ+tSullkgI6infwsWgT5Ao0uWwa5bIIkfWf8HE+?= =?us-ascii?Q?pxcszpGrzR/c7/jBlR/J76DYGwIs3VYcLEjCLCpJaSAwuWDYiFdY8RuFytWj?= =?us-ascii?Q?7Q3Dt5xhO1DE/SwHKrcqtW9g/4V/SMXbGHwlU+B7jG0mjWrOwBueVjqtQ2/V?= =?us-ascii?Q?hpfe4IcLVauncCEiaJDs62OnSjELgidvhLDIHoJM/Fghx2vxH55S1M+f/MgV?= =?us-ascii?Q?WyndayhDYxw9xx9LP3ITd+w/Qnv071loTBtKqy0K7q8LoIZaDmmPHHca6UX0?= =?us-ascii?Q?wzZy7Hwhmelp5BcJEb7JOQZ1hMjkI47At7n0fO2s6e5c1qS7wU3XclKzscAh?= =?us-ascii?Q?PETNJ6/Qgk2ry1D6NyNdD5JScqutvh9JnP869jjJT7Qmxl0g1qKMxbOw/63w?= =?us-ascii?Q?/g=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: e03ab5e3-5636-4599-1b3b-08da91c3faff X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1632.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Sep 2022 18:00:14.4362 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: lsKaurdh2JsDLz517kilBA7UHlYS+L+CnQYzloONPm7UWqsb5ATmiEJXM5XAyiyq/DZfPQmbB9MDkn/453Ov02U0pgwVTmJaV6D61nBEY1U= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB0011 X-OriginatorOrg: intel.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed, Sep 07, 2022 at 04:33:17PM -0700, Radhakrishna Sripada wrote: > From: Matt Roper > > The part of the media and blitter engine contexts that we care about for > setting up an initial state are the same on MTL as they were on DG2 > (and PVC), so we need to update the driver conditions to re-use the DG2 > context table. > > For render/compute engines, the part of the context images are nearly > the same, although the layout had a very slight change --- one POSH > register was removed and the placement of some LRI/noops adjusted > slightly to compensate. > > v2: > - Dg2, mtl xcs offsets slightly vary. Use a separate offsets array(Bala) > - Drop unused registers in mtl rcs offsets.(Bala) > - Add missing nop in xcs offsets(Bala) > > Bspec: 46261, 46260, 45585 > Cc: Balasubramani Vivekanandan > Signed-off-by: Matt Roper > Signed-off-by: Radhakrishna Sripada > --- > drivers/gpu/drm/i915/gt/intel_lrc.c | 82 ++++++++++++++++++++++++++++- > 1 file changed, 80 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c > index 070cec4ff8a4..a2247d39bdb7 100644 > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > @@ -264,6 +264,39 @@ static const u8 dg2_xcs_offsets[] = { > END > }; > > +static const u8 mtl_xcs_offsets[] = { > + NOP(1), > + LRI(13, POSTED), > + REG16(0x244), > + REG(0x034), > + REG(0x030), > + REG(0x038), > + REG(0x03c), > + REG(0x168), > + REG(0x140), > + REG(0x110), > + REG(0x1c0), > + REG(0x1c4), > + REG(0x1c8), > + REG(0x180), > + REG16(0x2b4), > + NOP(1), Shouldn't this be NOP(4)? Matt > + > + NOP(1), > + LRI(9, POSTED), > + REG16(0x3a8), > + REG16(0x28c), > + REG16(0x288), > + REG16(0x284), > + REG16(0x280), > + REG16(0x27c), > + REG16(0x278), > + REG16(0x274), > + REG16(0x270), > + > + END > +}; > + > static const u8 gen8_rcs_offsets[] = { > NOP(1), > LRI(14, POSTED), > @@ -606,6 +639,47 @@ static const u8 dg2_rcs_offsets[] = { > END > }; > > +static const u8 mtl_rcs_offsets[] = { > + NOP(1), > + LRI(13, POSTED), > + REG16(0x244), > + REG(0x034), > + REG(0x030), > + REG(0x038), > + REG(0x03c), > + REG(0x168), > + REG(0x140), > + REG(0x110), > + REG(0x1c0), > + REG(0x1c4), > + REG(0x1c8), > + REG(0x180), > + REG16(0x2b4), > + > + NOP(1), > + LRI(9, POSTED), > + REG16(0x3a8), > + REG16(0x28c), > + REG16(0x288), > + REG16(0x284), > + REG16(0x280), > + REG16(0x27c), > + REG16(0x278), > + REG16(0x274), > + REG16(0x270), > + > + NOP(2), > + LRI(2, POSTED), > + REG16(0x5a8), > + REG16(0x5ac), > + > + NOP(6), > + LRI(1, 0), > + REG(0x0c8), > + > + END > +}; > + > #undef END > #undef REG16 > #undef REG > @@ -624,7 +698,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) > !intel_engine_has_relative_mmio(engine)); > > if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) { > - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) > + return mtl_rcs_offsets; > + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) > return dg2_rcs_offsets; > else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) > return xehp_rcs_offsets; > @@ -637,7 +713,9 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine) > else > return gen8_rcs_offsets; > } else { > - if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) > + if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 70)) > + return mtl_xcs_offsets; > + else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) > return dg2_xcs_offsets; > else if (GRAPHICS_VER(engine->i915) >= 12) > return gen12_xcs_offsets; > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation