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> > - if (DISPLAY_VER(dev_priv) >= 12) > + if (DISPLAY_VER(dev_priv) >= 14) > + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), > + FECSTALL_DIS_DPTSTREAM_DPTTG, 0); > + else if (DISPLAY_VER(dev_priv) >= 12) > intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), > FECSTALL_DIS_DPTSTREAM_DPTTG, 0); > > @@ -1838,7 +1841,9 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > - i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder); > + enum transcoder transcoder = crtc_state->cpu_transcoder; > + i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) : > + CHICKEN_TRANS(transcoder); > u32 val; > > val = intel_de_read(dev_priv, reg); > @@ -4033,6 +4038,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > struct intel_display_power_domain_set power_domain_set = { }; > + i915_reg_t reg; > bool active; > u32 tmp; > > @@ -4124,7 +4130,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, > } > > if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { > - tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder)); > + reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) : > + CHICKEN_TRANS(pipe_config->cpu_transcoder); > + tmp = intel_de_read(dev_priv, reg); > > pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1; > } else { > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 13abe2b2170e..298004cae5a5 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -568,7 +568,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, > drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base, > drm_atomic_get_mst_payload_state(mst_state, connector->port)); > > - if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) > + if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) > + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0, > + FECSTALL_DIS_DPTSTREAM_DPTTG); > + else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) > intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, > FECSTALL_DIS_DPTSTREAM_DPTTG); > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 079b7d3d0c53..da2d0661b630 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1139,7 +1139,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > > if (intel_dp->psr.psr2_enabled) { > if (DISPLAY_VER(dev_priv) == 9) > - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, > + intel_de_rmw(dev_priv, > + CHICKEN_TRANS(cpu_transcoder), 0, This whitespace-only change on a non-MTL codepath doesn't look necessary. > PSR2_VSC_ENABLE_PROG_HEADER | > PSR2_ADD_VERTICAL_LINE_COUNT); > > @@ -1149,7 +1150,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > * cause issues if non-supported panels are used. > */ > if (IS_ALDERLAKE_P(dev_priv)) > - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, > + intel_de_rmw(dev_priv, > + CHICKEN_TRANS(cpu_transcoder), 0, Ditto. > ADLP_1_BASED_X_GRANULARITY); > > /* Wa_16011168373:adl-p */ > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index f9237586ab4f..8be7685e8a3e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5717,17 +5717,30 @@ > #define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3) > #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B) > > +#define _MTL_CHICKEN_TRANS_A 0x604e0 > +#define _MTL_CHICKEN_TRANS_B 0x614e0 > +#define _MTL_CHICKEN_TRANS_C 0x624e0 > +#define _MTL_CHICKEN_TRANS_D 0x634e0 > + > #define _CHICKEN_TRANS_A 0x420c0 > #define _CHICKEN_TRANS_B 0x420c4 > #define _CHICKEN_TRANS_C 0x420c8 > #define _CHICKEN_TRANS_EDP 0x420cc > #define _CHICKEN_TRANS_D 0x420d8 > -#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ > - [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ > - [TRANSCODER_A] = _CHICKEN_TRANS_A, \ > - [TRANSCODER_B] = _CHICKEN_TRANS_B, \ > - [TRANSCODER_C] = _CHICKEN_TRANS_C, \ > - [TRANSCODER_D] = _CHICKEN_TRANS_D)) > + > +#define CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ Nitpick: there's an extra space between 'define' and the register name that shouldn't be there (same with the MTL definition below). It looks like some of the subsequent register definitions in i915_reg.h are misformatted, but we shouldn't copy that mistake here. > + [TRANSCODER_EDP] = _CHICKEN_TRANS_EDP, \ > + [TRANSCODER_A] = _CHICKEN_TRANS_A, \ > + [TRANSCODER_B] = _CHICKEN_TRANS_B, \ > + [TRANSCODER_C] = _CHICKEN_TRANS_C, \ > + [TRANSCODER_D] = _CHICKEN_TRANS_D)) > + > +#define MTL_CHICKEN_TRANS(trans) _MMIO(_PICK((trans), \ > + [TRANSCODER_A] = _MTL_CHICKEN_TRANS_A, \ > + [TRANSCODER_B] = _MTL_CHICKEN_TRANS_B, \ > + [TRANSCODER_C] = _MTL_CHICKEN_TRANS_C, \ > + [TRANSCODER_D] = _MTL_CHICKEN_TRANS_D)) The registers are equally-spaced and there's no edp transcoder anymore, so this definition can be simplified down to just #define MTL_CHICKEN_TRANS _MMIO_TRANS((trans), \ _MTL_CHICKEN_TRANS_A, \ _MTL_CHICKEN_TRANS_B) and we can drop the definitions of _MTL_CHICKEN_TRANS_C and _MTL_CHICKEN_TRANS_D. Matt > + > #define HSW_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) > #define HSW_FRAME_START_DELAY(x) REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x) > #define VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */ > -- > 2.34.1 > -- Matt Roper Graphics Software Engineer VTT-OSGC Platform Enablement Intel Corporation