From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB048C6FA8E for ; Sat, 24 Sep 2022 14:45:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 79A6910E084; Sat, 24 Sep 2022 14:45:02 +0000 (UTC) Received: from relay02.th.seeweb.it (relay02.th.seeweb.it [5.144.164.163]) by gabe.freedesktop.org (Postfix) with ESMTPS id F0EAF10E051 for ; Sat, 24 Sep 2022 14:44:56 +0000 (UTC) Received: from [192.168.1.101] (95.49.29.188.neoplus.adsl.tpnet.pl [95.49.29.188]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by m-r1.th.seeweb.it (Postfix) with ESMTPSA id F19C01F58D; Sat, 24 Sep 2022 16:44:52 +0200 (CEST) Message-ID: Date: Sat, 24 Sep 2022 16:44:51 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.0 Subject: Re: [PATCH v2 2/2] drm/msm/dsi: Add phy configuration for QCM2290 To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski References: <20220924085129.161086-1-dmitry.baryshkov@linaro.org> <20220924085129.161086-3-dmitry.baryshkov@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20220924085129.161086-3-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Loic Poulain , David Airlie , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 24.09.2022 10:51, Dmitry Baryshkov wrote: > From: Loic Poulain > > The QCM2290 SoC a the 14nm (V2.0) single DSI phy. The platform is not > fully compatible with the standard 14nm PHY, so it requires a separate > compatible and config entry. > > Signed-off-by: Loic Poulain > [DB: changed compat to follow the agreed scheme, rebased and updated commit msg] > Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Konrad > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 ++ > drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + > drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 17 +++++++++++++++++ > 3 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > index 7fc0975cb869..724d5fa0788a 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c > @@ -553,6 +553,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { > .data = &dsi_phy_14nm_660_cfgs }, > { .compatible = "qcom,dsi-phy-14nm-8953", > .data = &dsi_phy_14nm_8953_cfgs }, > + { .compatible = "qcom,qcm2290-dsi-phy-14nm", > + .data = &dsi_phy_14nm_2290_cfgs }, > #endif > #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY > { .compatible = "qcom,dsi-phy-10nm", > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > index 60a99c6525b2..1096afedd616 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h > @@ -50,6 +50,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; > +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; > extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > index 0f8f4ca46429..9f488adea7f5 100644 > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c > @@ -1081,3 +1081,20 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_8953_cfgs = { > .io_start = { 0x1a94400, 0x1a96400 }, > .num_dsi_phy = 2, > }; > + > +const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs = { > + .has_phy_lane = true, > + .regulator_data = dsi_phy_14nm_17mA_regulators, > + .num_regulators = ARRAY_SIZE(dsi_phy_14nm_17mA_regulators), > + .ops = { > + .enable = dsi_14nm_phy_enable, > + .disable = dsi_14nm_phy_disable, > + .pll_init = dsi_pll_14nm_init, > + .save_pll_state = dsi_14nm_pll_save_state, > + .restore_pll_state = dsi_14nm_pll_restore_state, > + }, > + .min_pll_rate = VCO_MIN_RATE, > + .max_pll_rate = VCO_MAX_RATE, > + .io_start = { 0x5e94400 }, > + .num_dsi_phy = 1, > +};