From mboxrd@z Thu Jan 1 00:00:00 1970
From: bugzilla-daemon@freedesktop.org
Subject: [Bug 110208] New GPU sysfs Power State Interface for custom
pp_od_clk_voltage
Date: Wed, 20 Mar 2019 11:50:50 +0000
Message-ID:
References:
Mime-Version: 1.0
Content-Type: multipart/mixed; boundary="===============0580330632=="
Return-path:
Received: from culpepper.freedesktop.org (culpepper.freedesktop.org
[131.252.210.165])
by gabe.freedesktop.org (Postfix) with ESMTP id B20C889D42
for ; Wed, 20 Mar 2019 11:50:49 +0000 (UTC)
In-Reply-To:
List-Unsubscribe: ,
List-Archive:
List-Post:
List-Help:
List-Subscribe: ,
Errors-To: dri-devel-bounces@lists.freedesktop.org
Sender: "dri-devel"
To: dri-devel@lists.freedesktop.org
List-Id: dri-devel@lists.freedesktop.org
--===============0580330632==
Content-Type: multipart/alternative; boundary="15530826490.feE1.21174"
Content-Transfer-Encoding: 7bit
--15530826490.feE1.21174
Date: Wed, 20 Mar 2019 11:50:49 +0000
MIME-Version: 1.0
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://bugs.freedesktop.org/
Auto-Submitted: auto-generated
https://bugs.freedesktop.org/show_bug.cgi?id=3D110208
--- Comment #1 from famo ---
Link to documentation:
https://dri.freedesktop.org/docs/drm/gpu/amdgpu.html#power-dpm-force-perfor=
mance-level
Quote:
pp_od_clk_voltage
The amdgpu driver provides a sysfs API for adjusting the clocks and voltage=
s in
each power level within a power state. The pp_od_clk_voltage is used for th=
is.
< For Vega10 and previous ASICs >
Reading the file will display:
a list of engine clock levels and voltages labeled OD_SCLK
a list of memory clock levels and voltages labeled OD_MCLK
a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
To manually adjust these settings, first select manual using
power_dpm_force_performance_level. ...
--=20
You are receiving this mail because:
You are the assignee for the bug.=
--15530826490.feE1.21174
Date: Wed, 20 Mar 2019 11:50:49 +0000
MIME-Version: 1.0
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
X-Bugzilla-URL: http://bugs.freedesktop.org/
Auto-Submitted: auto-generated
Commen=
t # 1
on bug 11020=
8
from famo
Link to documentation:
https://dri.freedesktop.org/docs/drm/gpu/amdgpu.htm=
l#power-dpm-force-performance-level
Quote:
pp_od_clk_voltage
The amdgpu driver provides a sysfs API for adjusting the clocks and voltage=
s in
each power level within a power state. The pp_od_clk_voltage is used for th=
is.
< For Vega10 and previous ASICs >
Reading the file will display:
a list of engine clock levels and voltages labeled OD_SCLK
a list of memory clock levels and voltages labeled OD_MCLK
a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
To manually adjust these settings, first select manual using
power_dpm_force_performance_level. ...
You are receiving this mail because:
- You are the assignee for the bug.
=
--15530826490.feE1.21174--
--===============0580330632==
Content-Type: text/plain; charset="utf-8"
MIME-Version: 1.0
Content-Transfer-Encoding: base64
Content-Disposition: inline
X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJpLWRldmVs
IG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz
dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVs
--===============0580330632==--