From: Ramalingam C <ramalingam.c@intel.com>
To: "Daniel Vetter" <daniel@ffwll.ch>,
"Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
rodrigo.vivi@intel.com
Subject: Re: [PATCH v2 3/4] drm/i915: Check hdcp key loadability
Date: Wed, 11 Apr 2018 13:57:15 +0530 [thread overview]
Message-ID: <cade7bb7-d068-fb7d-3a03-c5912fcdbe02@intel.com> (raw)
In-Reply-To: <20180409082855.GJ31310@phenom.ffwll.local>
On Monday 09 April 2018 01:58 PM, Daniel Vetter wrote:
> On Fri, Apr 06, 2018 at 07:02:02PM +0300, Ville Syrjälä wrote:
>> On Mon, Apr 02, 2018 at 02:35:42PM +0530, Ramalingam C wrote:
>>>
>>> On Thursday 29 March 2018 07:54 PM, Ville Syrjälä wrote:
>>>> On Thu, Mar 29, 2018 at 07:39:07PM +0530, Ramalingam C wrote:
>>>>> HDCP1.4 key can be loaded, only when Power well #1 is enabled and cdclk
>>>>> is enabled. Using the I915 power well infrastruture, above requirement
>>>>> is verified.
>>>>>
>>>>> This patch enables the hdcp initialization for HSW, BDW, and BXT.
>>>>>
>>>>> v2:
>>>>> Choose the PW# based on the platform.
>>>>>
>>>>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>>>>> Reviewed-by: Sean Paul <seanpaul@chromium.org>
>>>>> ---
>>>>> drivers/gpu/drm/i915/intel_hdcp.c | 41 +++++++++++++++++++++++++++++++++++++--
>>>>> 1 file changed, 39 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
>>>>> index f77d956b2b18..d8af09b46a44 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_hdcp.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
>>>>> @@ -37,6 +37,43 @@ static int intel_hdcp_poll_ksv_fifo(struct intel_digital_port *intel_dig_port,
>>>>> return 0;
>>>>> }
>>>>>
>>>>> +static bool hdcp_key_loadable(struct drm_i915_private *dev_priv)
>>>>> +{
>>>>> + struct i915_power_domains *power_domains = &dev_priv->power_domains;
>>>>> + struct i915_power_well *power_well;
>>>>> + enum i915_power_well_id id;
>>>>> + bool enabled = false;
>>>>> +
>>>>> + /*
>>>>> + * On HSW and BDW, Display HW loads the Key as soon as Display resumes.
>>>>> + * On all BXT+, SW can load the keys only when the PW#1 is turned on.
>>>>> + */
>>>>> + if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>>>>> + id = HSW_DISP_PW_GLOBAL;
>>>>> + else
>>>>> + id = SKL_DISP_PW_1;
>>>>> +
>>>>> + mutex_lock(&power_domains->lock);
>>>>> +
>>>>> + /* PG1 (power well #1) needs to be enabled */
>>>>> + for_each_power_well(dev_priv, power_well) {
>>>>> + if (power_well->id == id) {
>>>>> + enabled = power_well->ops->is_enabled(dev_priv,
>>>>> + power_well);
>>>>> + break;
>>>>> + }
>>>>> + }
>>>>> + mutex_unlock(&power_domains->lock);
>>>>> +
>>>>> + /*
>>>>> + * Another req for hdcp key loadability is enabled state of pll for
>>>>> + * cdclk. Without active crtc we wont land here. So we are assuming that
>>>>> + * cdclk is already on.
>>>>> + */
>>>>> +
>>>>> + return enabled;
>>>>> +}
>>>>> +
>>>>> static void intel_hdcp_clear_keys(struct drm_i915_private *dev_priv)
>>>>> {
>>>>> I915_WRITE(HDCP_KEY_CONF, HDCP_CLEAR_KEYS_TRIGGER);
>>>>> @@ -615,8 +652,8 @@ static int _intel_hdcp_enable(struct intel_connector *connector)
>>>>> DRM_DEBUG_KMS("[%s:%d] HDCP is being enabled...\n",
>>>>> connector->base.name, connector->base.base.id);
>>>>>
>>>>> - if (!(I915_READ(SKL_FUSE_STATUS) & SKL_FUSE_PG_DIST_STATUS(1))) {
>>>>> - DRM_ERROR("PG1 is disabled, cannot load keys\n");
>>>>> + if (!hdcp_key_loadable(dev_priv)) {
>>>>> + DRM_ERROR("HDCP key Load is not possible\n");
>>>>> return -ENXIO;
>>>>> }
>>>> If you need the power well then why aren't you grabbing the correct
>>>> power domain reference somewhere?
>>> Ville,
>>>
>>> As HDCP is supposed to be enabled after the basic display is up, power well #1 is supposed to be enabled.
>>> If not that is mostly an error w.r.t HDCP.
>>>
>>> So at this point we just want to verify whether required PW is up and HDCP key can be loaded from the HW. Else fail the HDCP request.
>> So this is in practice dead code to deal with a hypothetical bug
>> elsewhere in the driver?
> Yeah looks like it should be wrapped in a WARN_ON, or maybe outright
> thrown out. The unclaimed mmio debug stuff will catch when this happens
> (or well, should).
> -Daniel
Ok. Intention of this patch was generalizing the existing SKL specific
PW check for all hdcp capable intel platforms.
Please suggest if this needs to be wrapped into WARN_ON or really want
to discard it.
--Ram
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next prev parent reply other threads:[~2018-04-11 8:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-29 14:09 [PATCH v2 0/4] HDCP1.4 fixes Ramalingam C
2018-03-29 14:09 ` [PATCH v2 1/4] drm/i915: Read HDCP R0 thrice in case of mismatch Ramalingam C
2018-03-29 14:35 ` Sean Paul
2018-04-02 9:08 ` Ramalingam C
2018-03-29 14:09 ` [PATCH v2 2/4] drm/i915: Read Vprime thrice incase " Ramalingam C
2018-03-29 14:38 ` Sean Paul
2018-04-02 9:16 ` Ramalingam C
2018-03-29 14:09 ` [PATCH v2 3/4] drm/i915: Check hdcp key loadability Ramalingam C
2018-03-29 14:24 ` Ville Syrjälä
2018-04-02 9:05 ` Ramalingam C
2018-04-06 16:02 ` Ville Syrjälä
2018-04-09 8:28 ` Daniel Vetter
2018-04-11 8:27 ` Ramalingam C [this message]
2018-04-13 15:49 ` Daniel Vetter
2018-03-29 14:09 ` [PATCH v2 4/4] drm/i915: Fix downstream dev count read Ramalingam C
2018-03-29 14:39 ` Sean Paul
2018-03-29 14:12 ` [PATCH v2 0/4] HDCP1.4 fixes Ramalingam C
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