Re: [LKP] Re: [drm/mgag200] e44e907dd8: phoronix-test-suite.glmark2.800x600.score -64.9% regression

[Rong Chen <rong.a.chen@intel.com>]

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On 6/16/20 11:10 AM, Rong Chen wrote:
>
>
> On 6/16/20 4:58 AM, Emil Velikov wrote:
>> Hi all,
>>
>> On Thu, 4 Jun 2020 at 08:11, kernel test robot 
>> <rong.a.chen@intel.com> wrote:
>>> Greeting,
>>>
>>> FYI, we noticed a -64.9% regression of 
>>> phoronix-test-suite.glmark2.800x600.score due to commit:
>>>
>> On one hand, I'm really happy to see performance testing happening
>> although this report is missing various crucial pieces of information.
>>
>>> commit: e44e907dd8f937313d35615d799d54162c56d173 ("[PATCH v3 05/15] 
>>> drm/mgag200: Split MISC register update into PLL selection, SYNC and 
>>> I/O")
>>> url: 
>>> https://github.com/0day-ci/linux/commits/Thomas-Zimmermann/drm-mgag200-Convert-to-atomic-modesetting/20200515-163744
>>> base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
>>>
>>> in testcase: phoronix-test-suite
>>> on test machine: 16 threads Intel(R) Xeon(R) CPU X5570 @ 2.93GHz 
>>> with 48G memory
>>> with following parameters:
>>>
>>>          need_x: true
>> Replace "need_x" with the Xorg version as seen in `Xorg -version'.
>
> # Xorg -version
> /bin/sh: warning: setlocale: LC_ALL: cannot change locale (en_US.UTF-8)
>
> X.Org X Server 1.20.4
> X Protocol Version 11, Revision 0
> Build Operating System: Linux 4.9.0-8-amd64 x86_64 Debian
> Current Operating System: Linux lkp-nhm-2ep1 
> 5.7.0-rc5-01428-ge44e907dd8f937 #1 SMP Tue Jun 2 19:51:38 CST 2020 x86_64
> Kernel command line:  ip=::::lkp-nhm-2ep1::dhcp 
> root=/dev/disk/by-id/wwn-0x55cd2e4123123127-part2 
> rootflags=subvol=debian-x86_64-phoronix 
> remote_rootfs=internal-lkp-server:/osimage/debian/debian-x86_64-phoronix 
> user=lkp 
> job=/lkp/jobs/scheduled/lkp-nhm-2ep1/phoronix-test-suite-performance-true-glmark2-1.1.0-ucode=0x1d-debian-x86_64-phoronix-e44e907dd8f937313d35615d799d54162c56d173-20200616-56456-1kgmjzm-0.yaml 
> ARCH=x86_64 kconfig=x86_64-rhel-7.6 
> branch=linux-devel/devel-hourly-2020051600 
> commit=e44e907dd8f937313d35615d799d54162c56d173 
> BOOT_IMAGE=/pkg/linux/x86_64-rhel-7.6/gcc-7/e44e907dd8f937313d35615d799d54162c56d173/vmlinuz-5.7.0-rc5-01428-ge44e907dd8f937 
> console=ttyS1,115200 console=tty0 max_uptime=3600 
> RESULT_ROOT=/result/phoronix-test-suite/performance-true-glmark2-1.1.0-ucode=0x1d/lkp-nhm-2ep1/debian-x86_64-phoronix/x86_64-rhel-7.6/gcc-7/e44e907dd8f937313d35615d799d54162c56d173/4 
> LKP_SERVER=inn nokaslr selinux=0 debug apic=debug sysrq_always_enabled 
> rcupdate.rcu_cpu_stall_timeout=100 net.ifnames=0 printk.devkmsg=on 
> panic=-1 softlockup_panic=1 nmi_watchdog=panic oops=panic 
> load_ramdisk=2 prompt_ramdisk=0 drbd.minor_count=8 
> systemd.log_level=err ignore_loglevel console=tty0 
> earlyprintk=ttyS0,115200 console=ttyS0,115200 vga=normal rw
> Build Date: 05 March 2019  08:11:12PM
> xorg-server 2:1.20.4-1 (https://www.debian.org/support)
> Current version of pixman: 0.36.0
>         Before reporting problems, check http://wiki.x.org
>         to make sure that you have the latest version.
>
>>
>>>          test: glmark2-1.1.0
>>>          cpufreq_governor: performance
>>>          ucode: 0x1d
>>>
>>> test-description: The Phoronix Test Suite is the most comprehensive 
>>> testing and benchmarking platform available that provides an 
>>> extensible framework for which new tests can be easily added.
>>> test-url: http://www.phoronix-test-suite.com/
>>>
>> Please remove the test description and url. They don't add any value.
>>
>> Mention which Mesa version is used as well as on what GPU. The output
>> of lspci and glxinfo will help here.
>
> Attached please find the outputs of lspci and glxinfo

Sorry, the previous lspci is not correct, please find it in this attachment.

Best Regards,
Rong Chen

>
>>
>> For this particular test - there is no Mesa/upstream driver for this
>> GPU, so I imagine one of the swrast drivers was used. Which one -
>> swrast (classic, softpipe, llvmpipe, swr) or kms_swrast.
>> The output of `LD_DEBUG=libs glxinfo  |& grep _dri.so` will help here.
>
> # LD_DEBUG=libs glxinfo  |& grep _dri.so
>       2132:     calling init: /usr/lib/i386-linux-gnu/dri/swrast_dri.so
>       2132:     calling fini: 
> /usr/lib/i386-linux-gnu/dri/swrast_dri.so [0]
>
> Best Regards,
> Rong Chen
>
>>
>>> commit:
>>>    bef2303526 ("drm/mgag200: Move mode-setting code into separate 
>>> helper function")
>>>    e44e907dd8 ("drm/mgag200: Split MISC register update into PLL 
>>> selection, SYNC and I/O")
>>>
>> Actually the offending commit has a subtle change of behaviour - it
>> adds an extra MGAREG_MISC_RAMMAPEN.
>> That is not documented and I've failed to spot it during review.
>>
>> Thomas - shall we revert that line in itself or at least add an inline
>> comment why it is needed?
>>
>>>    100 
>>> +---------------------------------------------------------------------+
>>>     90 |-+    +      +   +.+      +    +     +    +      + 
>>> :               |
>>>        | :    :      :   : :      :    :     :    :      : 
>>> :               |
>>>     80 |-:    :      :   : :      :    :     :    :      : 
>>> :               |
>>>     70 |-::   :     ::   :  :     :   ::     ::   :     :: 
>>> :                |
>>>        |: :  : :    : : :   :    : :  : :   : :  : :    : : 
>>> :                |
>>>     60 |:+:  : :    : : :   :    : :  : :   : :  : :    : : 
>>> :                |
>>>     50 |:+:  : :    : : :   :    : :  : :   : :  : :    : : 
>>> :                |
>>>     40 |:+ : : :   :  : :    :   : : :  :   :  : : :   :  : 
>>> :                |
>>>        |:  : : :   :  : :    :   : : :  :   :  : : :   :  : :O      
>>> O O O  O |
>>>     30 |:+ : : :   :  : :    :   : : :  :   :  : : :   :  : 
>>> :                |
>>>     20 |-+ ::   :  :   :     :  :   ::   : :   ::   :  : O 
>>> :                 |
>>>        |    :   : :    :      : :   :    : :    :   : : 
>>> :                 |
>>>     10 |-+  :   : :    :      : :   :    : :    :   : : 
>>> :                 |
>>>      0 
>>> +---------------------------------------------------------------------+
>>>
>>>
>>>                     phoronix-test-suite.glmark2.1024x768.score
>>>
>>>    70 
>>> +----------------------------------------------------------------------+ 
>>>
>>>       | +    +      +   +..+     +    +      +    +     + 
>>> +.+             |
>>>    60 |-:    :      :   :  :     :    :      :    :     : 
>>> :               |
>>>       | :    :      :   :  :     :    :      :    :     : 
>>> :               |
>>>    50 |-::   :     ::   :  :     ::   :      :   ::     :: 
>>> :               |
>>>       |: :  : :    : : :    :   : :  : :    : :  : :   : : 
>>> :                |
>>>    40 |:+:  : :    : : :    :   : :  : :    : :  : :   : : 
>>> :                |
>>>       |: :  : :    : : :    :   : :  : :    : :  : :   : : :         
>>> O      |
>>>    30 |:+ : : :   :  : :    :   :  : : :    : : :  :   :  : :O      
>>> O   O  O |
>>>       |:  : : :   :  : :    :   :  : : :    : : :  :   :  : 
>>> :                |
>>>    20 |:+ : : :   :  : :    :   :  : : :    : : :  :   :  : 
>>> :                |
>>>       |   ::   :  :   :      : :   ::   :  :   ::   : : O 
>>> ::                 |
>>>    10 |-+  :   : :    :      : :    :   :  :   :    : : 
>>> :                 |
>>>       |    :   : :  O :    O : : O  :   :  : O :    : : 
>>> :                 |
>>>     0 
>>> +----------------------------------------------------------------------+ 
>>>
>>>
>>>
>>> [*] bisect-good sample
>>> [O] bisect-bad  sample
>>>
>> Hmm I must be going blind - there isn't even a single * in either of 
>> the graphs.
>> Or perhaps my eyesight is fine and the legend or the graphs need fixing.
>>
>> HTH
>> -Emil
>
>
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[-- Attachment #2: lspci --]
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00:00.0 Host bridge: Intel Corporation 5520 I/O Hub to ESI Port (rev 13)
00:01.0 PCI bridge: Intel Corporation 5520/5500/X58 I/O Hub PCI Express Root Port 1 (rev 13)
00:09.0 PCI bridge: Intel Corporation 7500/5520/5500/X58 I/O Hub PCI Express Root Port 9 (rev 13)
00:0a.0 PCI bridge: Intel Corporation 7500/5520/5500/X58 I/O Hub PCI Express Root Port 10 (rev 13)
00:10.0 PIC: Intel Corporation 7500/5520/5500/X58 Physical and Link Layer Registers Port 0 (rev 13)
00:10.1 PIC: Intel Corporation 7500/5520/5500/X58 Routing and Protocol Layer Registers Port 0 (rev 13)
00:11.0 PIC: Intel Corporation 7500/5520/5500 Physical and Link Layer Registers Port 1 (rev 13)
00:11.1 PIC: Intel Corporation 7500/5520/5500 Routing & Protocol Layer Register Port 1 (rev 13)
00:13.0 PIC: Intel Corporation 7500/5520/5500/X58 I/O Hub I/OxAPIC Interrupt Controller (rev 13)
00:14.0 PIC: Intel Corporation 7500/5520/5500/X58 I/O Hub System Management Registers (rev 13)
00:14.1 PIC: Intel Corporation 7500/5520/5500/X58 I/O Hub GPIO and Scratch Pad Registers (rev 13)
00:14.2 PIC: Intel Corporation 7500/5520/5500/X58 I/O Hub Control Status and RAS Registers (rev 13)
00:14.3 PIC: Intel Corporation 7500/5520/5500/X58 I/O Hub Throttle Registers (rev 13)
00:15.0 PIC: Intel Corporation 7500/5520/5500/X58 Trusted Execution Technology Registers (rev 13)
00:16.0 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.1 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.2 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.3 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.4 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.5 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.6 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:16.7 System peripheral: Intel Corporation 5520/5500/X58 Chipset QuickData Technology Device (rev 13)
00:1a.0 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #4
00:1a.1 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #5
00:1a.2 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #6
00:1a.7 USB controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #2
00:1c.0 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 1
00:1c.4 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 5
00:1c.5 PCI bridge: Intel Corporation 82801JI (ICH10 Family) PCI Express Root Port 6
00:1d.0 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #1
00:1d.1 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #2
00:1d.2 USB controller: Intel Corporation 82801JI (ICH10 Family) USB UHCI Controller #3
00:1d.7 USB controller: Intel Corporation 82801JI (ICH10 Family) USB2 EHCI Controller #1
00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 90)
00:1f.0 ISA bridge: Intel Corporation 82801JIR (ICH10R) LPC Interface Controller
00:1f.2 IDE interface: Intel Corporation 82801JI (ICH10 Family) 4 port SATA IDE Controller #1
00:1f.3 SMBus: Intel Corporation 82801JI (ICH10 Family) SMBus Controller
00:1f.5 IDE interface: Intel Corporation 82801JI (ICH10 Family) 2 port SATA IDE Controller #2
01:00.0 Ethernet controller: Intel Corporation 82575EB Gigabit Network Connection (rev 02)
01:00.1 Ethernet controller: Intel Corporation 82575EB Gigabit Network Connection (rev 02)
04:00.0 SCSI storage controller: LSI Logic / Symbios Logic SAS1078 PCI-Express Fusion-MPT SAS (rev 04)
05:00.0 VGA compatible controller: Matrox Electronics Systems Ltd. MGA G200e [Pilot] ServerEngines (SEP1) (rev 02)
fe:00.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers (rev 05)
fe:00.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture System Address Decoder (rev 05)
fe:02.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 0 (rev 05)
fe:02.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 0 (rev 05)
fe:02.4 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 1 (rev 05)
fe:02.5 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 1 (rev 05)
fe:03.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller (rev 05)
fe:03.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Target Address Decoder (rev 05)
fe:03.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller RAS Registers (rev 05)
fe:03.4 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Test Registers (rev 05)
fe:04.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Control Registers (rev 05)
fe:04.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Address Registers (rev 05)
fe:04.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Rank Registers (rev 05)
fe:04.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers (rev 05)
fe:05.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Control Registers (rev 05)
fe:05.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Address Registers (rev 05)
fe:05.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Rank Registers (rev 05)
fe:05.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers (rev 05)
fe:06.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Control Registers (rev 05)
fe:06.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Address Registers (rev 05)
fe:06.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Rank Registers (rev 05)
fe:06.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers (rev 05)
ff:00.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture Generic Non-Core Registers (rev 05)
ff:00.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QuickPath Architecture System Address Decoder (rev 05)
ff:02.0 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 0 (rev 05)
ff:02.1 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 0 (rev 05)
ff:02.4 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Link 1 (rev 05)
ff:02.5 Host bridge: Intel Corporation Xeon 5500/Core i7 QPI Physical 1 (rev 05)
ff:03.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller (rev 05)
ff:03.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Target Address Decoder (rev 05)
ff:03.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller RAS Registers (rev 05)
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ff:04.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Control Registers (rev 05)
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ff:04.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Rank Registers (rev 05)
ff:04.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 0 Thermal Control Registers (rev 05)
ff:05.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Control Registers (rev 05)
ff:05.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Address Registers (rev 05)
ff:05.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Rank Registers (rev 05)
ff:05.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 1 Thermal Control Registers (rev 05)
ff:06.0 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Control Registers (rev 05)
ff:06.1 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Address Registers (rev 05)
ff:06.2 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Rank Registers (rev 05)
ff:06.3 Host bridge: Intel Corporation Xeon 5500/Core i7 Integrated Memory Controller Channel 2 Thermal Control Registers (rev 05)

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