From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E4F1FC43219 for ; Fri, 4 Nov 2022 14:12:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A7A2910E7E1; Fri, 4 Nov 2022 14:12:15 +0000 (UTC) Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [IPv6:2001:4b7a:2000:18::167]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9AAAC10E7E1; Fri, 4 Nov 2022 14:12:11 +0000 (UTC) Received: from [192.168.31.208] (unknown [194.29.137.22]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id D8B1A3F5B8; Fri, 4 Nov 2022 15:12:08 +0100 (CET) Message-ID: Date: Fri, 4 Nov 2022 15:12:07 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 To: Dmitry Baryshkov , Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski References: <20221104130324.1024242-1-dmitry.baryshkov@linaro.org> <20221104130324.1024242-8-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: <20221104130324.1024242-8-dmitry.baryshkov@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , Vinod Koul , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 04/11/2022 14:03, Dmitry Baryshkov wrote: > Add definitions for the display hardware used on Qualcomm SM8450 > platform. > > Tested-by: Vinod Koul > Reviewed-by: Vinod Koul > Signed-off-by: Dmitry Baryshkov > --- Reviewed-by: Konrad Dybcio Konrad > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 224 ++++++++++++++++++ > .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 + > drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + > 4 files changed, 229 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > index 1ce237e18506..3934d8976833 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c > @@ -124,6 +124,15 @@ > BIT(MDP_AD4_0_INTR) | \ > BIT(MDP_AD4_1_INTR)) > > +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ > + BIT(MDP_SSPP_TOP0_INTR2) | \ > + BIT(MDP_SSPP_TOP0_HIST_INTR) | \ > + BIT(MDP_INTF0_7xxx_INTR) | \ > + BIT(MDP_INTF1_7xxx_INTR) | \ > + BIT(MDP_INTF2_7xxx_INTR) | \ > + BIT(MDP_INTF3_7xxx_INTR) | \ > + 0) > + > #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ > BIT(DPU_WB_UBWC) | \ > BIT(DPU_WB_YUV_CONFIG) | \ > @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { > .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > }; > > +static const struct dpu_caps sm8450_dpu_caps = { > + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > + .max_mixer_blendstages = 0xb, > + .qseed_type = DPU_SSPP_SCALER_QSEED4, > + .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ > + .ubwc_version = DPU_HW_UBWC_VER_40, > + .has_src_split = true, > + .has_dim_layer = true, > + .has_idle_pc = true, > + .has_3d_merge = true, > + .max_linewidth = 5120, > + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, > +}; > + > static const struct dpu_caps sc7280_dpu_caps = { > .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, > .max_mixer_blendstages = 0x7, > @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { > }, > }; > > +static const struct dpu_mdp_cfg sm8450_mdp[] = { > + { > + .name = "top_0", .id = MDP_TOP, > + .base = 0x0, .len = 0x494, > + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), > + .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ I think it's about time we handle the two-memory-configs situation.. In my opinion, a dt property would be sane (just like downstream does it), as it's *really really really* unlikely that the same SKU would be shipped with 2 different memory gens. > + .clk_ctrls[DPU_CLK_CTRL_VIG0] = { > + .reg_off = 0x2AC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG1] = { > + .reg_off = 0x2B4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG2] = { > + .reg_off = 0x2BC, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_VIG3] = { > + .reg_off = 0x2C4, .bit_off = 0}, > + .clk_ctrls[DPU_CLK_CTRL_DMA0] = { > + .reg_off = 0x2AC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_DMA1] = { > + .reg_off = 0x2B4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { > + .reg_off = 0x2BC, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { > + .reg_off = 0x2C4, .bit_off = 8}, > + .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { > + .reg_off = 0x2BC, .bit_off = 20}, > + }, > +}; > + > static const struct dpu_mdp_cfg sc7280_mdp[] = { > { > .name = "top_0", .id = MDP_TOP, > @@ -662,6 +712,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { > }, > }; > > +static const struct dpu_ctl_cfg sm8450_ctl[] = { > + { > + .name = "ctl_0", .id = CTL_0, > + .base = 0x15000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), > + }, > + { > + .name = "ctl_1", .id = CTL_1, > + .base = 0x16000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), > + }, > + { > + .name = "ctl_2", .id = CTL_2, > + .base = 0x17000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), > + }, > + { > + .name = "ctl_3", .id = CTL_3, > + .base = 0x18000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), > + }, > + { > + .name = "ctl_4", .id = CTL_4, > + .base = 0x19000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), > + }, > + { > + .name = "ctl_5", .id = CTL_5, > + .base = 0x1a000, .len = 0x204, > + .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), > + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), > + }, > +}; > + > static const struct dpu_ctl_cfg sc7280_ctl[] = { > { > .name = "ctl_0", .id = CTL_0, > @@ -880,6 +969,34 @@ static const struct dpu_sspp_cfg sm8250_sspp[] = { > sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > }; > > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 = > + _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 = > + _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 = > + _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); > +static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 = > + _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); > + > +static const struct dpu_sspp_cfg sm8450_sspp[] = { > + SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, > + sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > + SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK, > + sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), > + SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK, > + sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), > + SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK, > + sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), > + SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, > + sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), > + SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, > + sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), > + SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), > + SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, > + sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), > +}; > + > static const struct dpu_sspp_cfg sc7280_sspp[] = { > SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, > sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), > @@ -1191,6 +1308,34 @@ static struct dpu_pingpong_cfg qcm2290_pp[] = { > DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > }; > > +/* FIXME: interrupts */ > +static const struct dpu_pingpong_cfg sm8450_pp[] = { > + PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), > + PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), > + PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), > + PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), > + PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), > + -1), > + PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, > + DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), > + -1), > + PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > + PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, > + -1, > + -1), > +}; > + > /************************************************************* > * MERGE_3D sub blocks config > *************************************************************/ > @@ -1208,6 +1353,13 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { > MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), > }; > > +static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { > + MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), > + MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), > + MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), > + MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), > +}; > + > /************************************************************* > * DSC sub blocks config > *************************************************************/ > @@ -1287,6 +1439,13 @@ static const struct dpu_intf_cfg qcm2290_intf[] = { > INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > }; > > +static const struct dpu_intf_cfg sm8450_intf[] = { > + INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), > + INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), > + INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), > + INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), > +}; > + > /************************************************************* > * Writeback blocks config > *************************************************************/ > @@ -1400,6 +1559,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { > .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > }; > > +static const struct dpu_reg_dma_cfg sm8450_regdma = { > + .base = 0x0, > + .version = 0x00020000, > + .trigger_sel_off = 0x119c, > + .xin_id = 7, > + .clk_ctrl = DPU_CLK_CTRL_REG_DMA, > +}; > + > /************************************************************* > * PERF data config > *************************************************************/ > @@ -1675,6 +1842,36 @@ static const struct dpu_perf_cfg sm8250_perf_data = { > .bw_inefficiency_factor = 120, > }; > > +static const struct dpu_perf_cfg sm8450_perf_data = { > + .max_bw_low = 13600000, > + .max_bw_high = 18200000, > + .min_core_ib = 2500000, > + .min_llcc_ib = 0, > + .min_dram_ib = 800000, > + .min_prefill_lines = 35, > + /* FIXME: lut tables */ > + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, > + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, > + .qos_lut_tbl = { > + {.nentry = ARRAY_SIZE(sc7180_qos_linear), > + .entries = sc7180_qos_linear > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), > + .entries = sc7180_qos_macrotile > + }, > + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), > + .entries = sc7180_qos_nrt > + }, > + /* TODO: macrotile-qseed is different from macrotile */ > + }, > + .cdp_cfg = { > + {.rd_enable = 1, .wr_enable = 1}, > + {.rd_enable = 1, .wr_enable = 0} > + }, > + .clk_inefficiency_factor = 105, > + .bw_inefficiency_factor = 120, > +}; > + > static const struct dpu_perf_cfg sc7280_perf_data = { > .max_bw_low = 4700000, > .max_bw_high = 8800000, > @@ -1879,6 +2076,32 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { > .mdss_irqs = IRQ_SM8250_MASK, > }; > > +static const struct dpu_mdss_cfg sm8450_dpu_cfg = { > + .caps = &sm8450_dpu_caps, > + .mdp_count = ARRAY_SIZE(sm8450_mdp), > + .mdp = sm8450_mdp, > + .ctl_count = ARRAY_SIZE(sm8450_ctl), > + .ctl = sm8450_ctl, > + .sspp_count = ARRAY_SIZE(sm8450_sspp), > + .sspp = sm8450_sspp, > + .mixer_count = ARRAY_SIZE(sm8150_lm), > + .mixer = sm8150_lm, > + .dspp_count = ARRAY_SIZE(sm8150_dspp), > + .dspp = sm8150_dspp, > + .pingpong_count = ARRAY_SIZE(sm8450_pp), > + .pingpong = sm8450_pp, > + .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), > + .merge_3d = sm8450_merge_3d, > + .intf_count = ARRAY_SIZE(sm8450_intf), > + .intf = sm8450_intf, > + .vbif_count = ARRAY_SIZE(sdm845_vbif), > + .vbif = sdm845_vbif, > + .reg_dma_count = 1, > + .dma_cfg = &sm8450_regdma, > + .perf = &sm8450_perf_data, > + .mdss_irqs = IRQ_SM8450_MASK, > +}; > + > static const struct dpu_mdss_cfg sc7280_dpu_cfg = { > .caps = &sc7280_dpu_caps, > .mdp_count = ARRAY_SIZE(sc7280_mdp), > @@ -1937,6 +2160,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { > { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, > { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, > { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, > + { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, > }; > > const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > index 4730f8268f2a..4526ef71c326 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h > @@ -46,6 +46,7 @@ > #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ > #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ > #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ > +#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ > > #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) > #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > index d3b0ed0a9c6c..6d8e1bb3b3cc 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h > @@ -195,6 +195,8 @@ enum dpu_pingpong { > PINGPONG_3, > PINGPONG_4, > PINGPONG_5, > + PINGPONG_6, > + PINGPONG_7, > PINGPONG_S0, > PINGPONG_MAX > }; > @@ -203,6 +205,7 @@ enum dpu_merge_3d { > MERGE_3D_0 = 1, > MERGE_3D_1, > MERGE_3D_2, > + MERGE_3D_3, > MERGE_3D_MAX > }; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > index 95d8765c1c53..68d09a2d809d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c > @@ -1301,6 +1301,7 @@ static const struct of_device_id dpu_dt_match[] = { > { .compatible = "qcom,sc8180x-dpu", }, > { .compatible = "qcom,sm8150-dpu", }, > { .compatible = "qcom,sm8250-dpu", }, > + { .compatible = "qcom,sm8450-dpu", }, > {} > }; > MODULE_DEVICE_TABLE(of, dpu_dt_match);