dri-devel.lists.freedesktop.org archive mirror
 help / color / mirror / Atom feed
From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Winkler, Tomas" <tomas.winkler@intel.com>,
	"Lubart, Vitaly" <vitaly.lubart@intel.com>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v4 10/15] drm/i915/dg2: setup HuC loading via GSC
Date: Fri, 9 Sep 2022 20:54:08 +0000	[thread overview]
Message-ID: <fbe275c83ce6f24e973f698ebedd0722880c05a3.camel@intel.com> (raw)
In-Reply-To: <20220909001612.728451-11-daniele.ceraolospurio@intel.com>

Nearly identical as before:
Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>


On Thu, 2022-09-08 at 17:16 -0700, Ceraolo Spurio, Daniele wrote:
> The GSC will perform both the load and the authentication, so we just
> need to check the auth bit after the GSC has replied.
> Since we require the PXP module to load the HuC, the earliest we can
> trigger the load is during the pxp_bind operation.
> 
> Note that GSC-loaded HuC survives GT reset, so we need to just mark it
> as ready when we re-init the GT HW.
> 
> V2: move setting of HuC fw error state to the failure path of the HuC
> auth function, so it covers both the legacy and new auth flows
> V4:
> 1. Fix typo in the commit message
> 2. style fix in intel_huc_wait_for_auth_complete()
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
> Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com> #v2
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_huc.c    | 41 +++++++++++++++--------
>  drivers/gpu/drm/i915/gt/uc/intel_huc.h    |  2 ++
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c | 34 +++++++++++++++++++
>  drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h |  1 +
>  drivers/gpu/drm/i915/pxp/intel_pxp_tee.c  | 14 +++++++-
>  5 files changed, 77 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.c b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> index 3bb8838e325a..f0188931d8e4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.c
> @@ -125,6 +125,28 @@ void intel_huc_fini(struct intel_huc *huc)
>  	intel_uc_fw_fini(&huc->fw);
>  }
>  
> +int intel_huc_wait_for_auth_complete(struct intel_huc *huc)
> +{
> +	struct intel_gt *gt = huc_to_gt(huc);
> +	int ret;
> +
> +	ret = __intel_wait_for_register(gt->uncore,
> +					huc->status.reg,
> +					huc->status.mask,
> +					huc->status.value,
> +					2, 50, NULL);
> +
> +	if (ret) {
> +		drm_err(&gt->i915->drm, "HuC: Firmware not verified %d\n", ret);
> +		intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
> +		return ret;
> +	}
> +
> +	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
> +	drm_info(&gt->i915->drm, "HuC authenticated\n");
> +	return 0;
> +}
> +
>  /**
>   * intel_huc_auth() - Authenticate HuC uCode
>   * @huc: intel_huc structure
> @@ -161,27 +183,18 @@ int intel_huc_auth(struct intel_huc *huc)
>  	}
>  
>  	/* Check authentication status, it should be done by now */
> -	ret = __intel_wait_for_register(gt->uncore,
> -					huc->status.reg,
> -					huc->status.mask,
> -					huc->status.value,
> -					2, 50, NULL);
> -	if (ret) {
> -		DRM_ERROR("HuC: Firmware not verified %d\n", ret);
> +	ret = intel_huc_wait_for_auth_complete(huc);
> +	if (ret)
>  		goto fail;
> -	}
>  
> -	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
> -	drm_info(&gt->i915->drm, "HuC authenticated\n");
>  	return 0;
>  
>  fail:
>  	i915_probe_error(gt->i915, "HuC: Authentication failed %d\n", ret);
> -	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_LOAD_FAIL);
>  	return ret;
>  }
>  
> -static bool huc_is_authenticated(struct intel_huc *huc)
> +bool intel_huc_is_authenticated(struct intel_huc *huc)
>  {
>  	struct intel_gt *gt = huc_to_gt(huc);
>  	intel_wakeref_t wakeref;
> @@ -223,7 +236,7 @@ int intel_huc_check_status(struct intel_huc *huc)
>  		break;
>  	}
>  
> -	return huc_is_authenticated(huc);
> +	return intel_huc_is_authenticated(huc);
>  }
>  
>  void intel_huc_update_auth_status(struct intel_huc *huc)
> @@ -231,7 +244,7 @@ void intel_huc_update_auth_status(struct intel_huc *huc)
>  	if (!intel_uc_fw_is_loadable(&huc->fw))
>  		return;
>  
> -	if (huc_is_authenticated(huc))
> +	if (intel_huc_is_authenticated(huc))
>  		intel_uc_fw_change_status(&huc->fw,
>  					  INTEL_UC_FIRMWARE_RUNNING);
>  }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc.h b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> index d7e25b6e879e..51f9d96a3ca3 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc.h
> @@ -26,8 +26,10 @@ void intel_huc_init_early(struct intel_huc *huc);
>  int intel_huc_init(struct intel_huc *huc);
>  void intel_huc_fini(struct intel_huc *huc);
>  int intel_huc_auth(struct intel_huc *huc);
> +int intel_huc_wait_for_auth_complete(struct intel_huc *huc);
>  int intel_huc_check_status(struct intel_huc *huc);
>  void intel_huc_update_auth_status(struct intel_huc *huc);
> +bool intel_huc_is_authenticated(struct intel_huc *huc);
>  
>  static inline int intel_huc_sanitize(struct intel_huc *huc)
>  {
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> index 9d6ab1e01639..4f246416db17 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.c
> @@ -3,9 +3,43 @@
>   * Copyright © 2014-2019 Intel Corporation
>   */
>  
> +#include "gt/intel_gsc.h"
>  #include "gt/intel_gt.h"
> +#include "intel_huc.h"
>  #include "intel_huc_fw.h"
>  #include "i915_drv.h"
> +#include "pxp/intel_pxp_huc.h"
> +
> +int intel_huc_fw_load_and_auth_via_gsc(struct intel_huc *huc)
> +{
> +	int ret;
> +
> +	if (!intel_huc_is_loaded_by_gsc(huc))
> +		return -ENODEV;
> +
> +	if (!intel_uc_fw_is_loadable(&huc->fw))
> +		return -ENOEXEC;
> +
> +	/*
> +	 * If we abort a suspend, HuC might still be loaded when the mei
> +	 * component gets re-bound and this function called again. If so, just
> +	 * mark the HuC as loaded.
> +	 */
> +	if (intel_huc_is_authenticated(huc)) {
> +		intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_RUNNING);
> +		return 0;
> +	}
> +
> +	GEM_WARN_ON(intel_uc_fw_is_loaded(&huc->fw));
> +
> +	ret = intel_pxp_huc_load_and_auth(&huc_to_gt(huc)->pxp);
> +	if (ret)
> +		return ret;
> +
> +	intel_uc_fw_change_status(&huc->fw, INTEL_UC_FIRMWARE_TRANSFERRED);
> +
> +	return intel_huc_wait_for_auth_complete(huc);
> +}
>  
>  /**
>   * intel_huc_fw_upload() - load HuC uCode to device via DMA transfer
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
> index 12f264ee3e0b..db42e238b45f 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h
> @@ -8,6 +8,7 @@
>  
>  struct intel_huc;
>  
> +int intel_huc_fw_load_and_auth_via_gsc(struct intel_huc *huc);
>  int intel_huc_fw_upload(struct intel_huc *huc);
>  
>  #endif
> diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> index e0d09455a92e..00433f59e2c8 100644
> --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c
> @@ -14,6 +14,7 @@
>  #include "intel_pxp_session.h"
>  #include "intel_pxp_tee.h"
>  #include "intel_pxp_tee_interface.h"
> +#include "intel_pxp_huc.h"
>  
>  static inline struct intel_pxp *i915_dev_to_pxp(struct device *i915_kdev)
>  {
> @@ -126,13 +127,24 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
>  {
>  	struct drm_i915_private *i915 = kdev_to_i915(i915_kdev);
>  	struct intel_pxp *pxp = i915_dev_to_pxp(i915_kdev);
> +	struct intel_uc *uc = &pxp_to_gt(pxp)->uc;
>  	intel_wakeref_t wakeref;
> +	int ret = 0;
>  
>  	mutex_lock(&pxp->tee_mutex);
>  	pxp->pxp_component = data;
>  	pxp->pxp_component->tee_dev = tee_kdev;
>  	mutex_unlock(&pxp->tee_mutex);
>  
> +	if (intel_uc_uses_huc(uc) && intel_huc_is_loaded_by_gsc(&uc->huc)) {
> +		with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
> +			/* load huc via pxp */
> +			ret = intel_huc_fw_load_and_auth_via_gsc(&uc->huc);
> +			if (ret < 0)
> +				drm_err(&i915->drm, "failed to load huc via gsc %d\n", ret);
> +		}
> +	}
> +
>  	/* if we are suspended, the HW will be re-initialized on resume */
>  	wakeref = intel_runtime_pm_get_if_in_use(&i915->runtime_pm);
>  	if (!wakeref)
> @@ -144,7 +156,7 @@ static int i915_pxp_tee_component_bind(struct device *i915_kdev,
>  
>  	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
>  
> -	return 0;
> +	return ret;
>  }
>  
>  static void i915_pxp_tee_component_unbind(struct device *i915_kdev,
> -- 
> 2.37.2
> 


  reply	other threads:[~2022-09-09 20:54 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-09  0:15 [PATCH v4 00/15] drm/i915: HuC loading for DG2 Daniele Ceraolo Spurio
2022-09-09  0:15 ` [PATCH v4 01/15] mei: add support to GSC extended header Daniele Ceraolo Spurio
2022-09-09  6:11   ` Greg Kroah-Hartman
2022-09-09  6:29     ` Winkler, Tomas
2022-09-09  0:15 ` [PATCH v4 02/15] mei: bus: enable sending gsc commands Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 03/15] mei: adjust extended header kdocs Daniele Ceraolo Spurio
2022-09-09  6:12   ` Greg Kroah-Hartman
2022-09-09  0:16 ` [PATCH v4 04/15] mei: bus: extend bus API to support command streamer API Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 05/15] mei: pxp: add command streamer API to the PXP driver Daniele Ceraolo Spurio
2022-09-09  6:14   ` Greg Kroah-Hartman
2022-09-09  6:38     ` Winkler, Tomas
2022-09-09  6:42       ` Greg Kroah-Hartman
2022-09-12  9:59         ` Winkler, Tomas
2022-09-12 14:25           ` Greg Kroah-Hartman
2022-09-09  0:16 ` [PATCH v4 06/15] mei: pxp: support matching with a gfx discrete card Daniele Ceraolo Spurio
2022-09-09  6:16   ` Greg Kroah-Hartman
2022-09-09  6:51     ` Winkler, Tomas
2022-09-09  6:59       ` Greg Kroah-Hartman
2022-09-09  9:21         ` Winkler, Tomas
2022-09-09 10:19           ` Greg Kroah-Hartman
2022-09-12 10:05             ` Winkler, Tomas
2022-09-09  0:16 ` [PATCH v4 07/15] drm/i915/pxp: load the pxp module when we have a gsc-loaded huc Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 08/15] drm/i915/pxp: implement function for sending tee stream command Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 09/15] drm/i915/pxp: add huc authentication and loading command Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 10/15] drm/i915/dg2: setup HuC loading via GSC Daniele Ceraolo Spurio
2022-09-09 20:54   ` Teres Alexis, Alan Previn [this message]
2022-09-09  0:16 ` [PATCH v4 11/15] drm/i915/huc: track delayed HuC load with a fence Daniele Ceraolo Spurio
2022-09-09 21:10   ` Teres Alexis, Alan Previn
2022-09-09  0:16 ` [PATCH v4 12/15] drm/i915/huc: stall media submission until HuC is loaded Daniele Ceraolo Spurio
2022-09-09 21:20   ` Ye, Tony
2022-09-09  0:16 ` [PATCH v4 13/15] drm/i915/huc: better define HuC status getparam possible return values Daniele Ceraolo Spurio
2022-09-09  0:16 ` [PATCH v4 14/15] drm/i915/huc: define gsc-compatible HuC fw for DG2 Daniele Ceraolo Spurio
2022-09-09 21:20   ` Ye, Tony
2022-09-10  0:18   ` Teres Alexis, Alan Previn
2022-09-09  0:16 ` [PATCH v4 15/15] HAX: drm/i915: force INTEL_MEI_GSC and INTEL_MEI_PXP on for CI Daniele Ceraolo Spurio
2022-09-09  0:22   ` Ceraolo Spurio, Daniele
2022-09-09  6:01 ` [PATCH v4 00/15] drm/i915: HuC loading for DG2 Winkler, Tomas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=fbe275c83ce6f24e973f698ebedd0722880c05a3.camel@intel.com \
    --to=alan.previn.teres.alexis@intel.com \
    --cc=daniele.ceraolospurio@intel.com \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=tomas.winkler@intel.com \
    --cc=vitaly.lubart@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).