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Thu, 10 Nov 2022 12:28:19 -0800 (PST) Received: from [10.10.15.130] ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id u2-20020a05651220c200b00499bf7605afsm10183lfr.143.2022.11.10.12.28.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 10 Nov 2022 12:28:19 -0800 (PST) Message-ID: Date: Thu, 10 Nov 2022 23:28:18 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v3 7/8] drm/msm/dpu: add support for SM8450 Content-Language: en-GB To: Konrad Dybcio , Andy Gross , Bjorn Andersson , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski References: <20221104130324.1024242-1-dmitry.baryshkov@linaro.org> <20221104130324.1024242-8-dmitry.baryshkov@linaro.org> From: Dmitry Baryshkov In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , Vinod Koul , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 04/11/2022 17:12, Konrad Dybcio wrote: > > On 04/11/2022 14:03, Dmitry Baryshkov wrote: >> Add definitions for the display hardware used on Qualcomm SM8450 >> platform. >> >> Tested-by: Vinod Koul >> Reviewed-by: Vinod Koul >> Signed-off-by: Dmitry Baryshkov >> --- > > Reviewed-by: Konrad Dybcio > > > Konrad > >>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    | 224 ++++++++++++++++++ >>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   1 + >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h   |   3 + >>   drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c       |   1 + >>   4 files changed, 229 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> index 1ce237e18506..3934d8976833 100644 >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c >> @@ -124,6 +124,15 @@ >>                 BIT(MDP_AD4_0_INTR) | \ >>                 BIT(MDP_AD4_1_INTR)) >> +#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ >> +             BIT(MDP_SSPP_TOP0_INTR2) | \ >> +             BIT(MDP_SSPP_TOP0_HIST_INTR) | \ >> +             BIT(MDP_INTF0_7xxx_INTR) | \ >> +             BIT(MDP_INTF1_7xxx_INTR) | \ >> +             BIT(MDP_INTF2_7xxx_INTR) | \ >> +             BIT(MDP_INTF3_7xxx_INTR) | \ >> +             0) >> + >>   #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ >>                BIT(DPU_WB_UBWC) | \ >>                BIT(DPU_WB_YUV_CONFIG) | \ >> @@ -367,6 +376,20 @@ static const struct dpu_caps sm8250_dpu_caps = { >>       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >>   }; >> +static const struct dpu_caps sm8450_dpu_caps = { >> +    .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >> +    .max_mixer_blendstages = 0xb, >> +    .qseed_type = DPU_SSPP_SCALER_QSEED4, >> +    .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ >> +    .ubwc_version = DPU_HW_UBWC_VER_40, >> +    .has_src_split = true, >> +    .has_dim_layer = true, >> +    .has_idle_pc = true, >> +    .has_3d_merge = true, >> +    .max_linewidth = 5120, >> +    .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, >> +}; >> + >>   static const struct dpu_caps sc7280_dpu_caps = { >>       .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, >>       .max_mixer_blendstages = 0x7, >> @@ -504,6 +527,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { >>       }, >>   }; >> +static const struct dpu_mdp_cfg sm8450_mdp[] = { >> +    { >> +    .name = "top_0", .id = MDP_TOP, >> +    .base = 0x0, .len = 0x494, >> +    .features = BIT(DPU_MDP_PERIPH_0_REMOVED), >> +    .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ > > I think it's about time we handle the two-memory-configs situation.. > > In my opinion, a dt property would be sane (just like downstream does > it), as it's > > *really really really* unlikely that the same SKU would be shipped with > 2 different memory gens. As it's really unlikely, I think we can drop the TODO comment completely until we phase a device with different memory type. WDYT? -- With best wishes Dmitry