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Fri, 9 Jun 2023 18:41:11 GMT Received: from akhilpo-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 9 Jun 2023 11:41:06 -0700 Date: Sat, 10 Jun 2023 00:11:03 +0530 From: Akhil P Oommen To: Konrad Dybcio Subject: Re: [PATCH v8 09/18] drm/msm/a6xx: Extend and explain UBWC config Message-ID: References: <20230223-topic-gmuwrapper-v8-0-69c68206609e@linaro.org> <20230223-topic-gmuwrapper-v8-9-69c68206609e@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20230223-topic-gmuwrapper-v8-9-69c68206609e@linaro.org> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: wrcCo9IbnIWKB3UaCZvgU6LcnLnjUO4h X-Proofpoint-ORIG-GUID: wrcCo9IbnIWKB3UaCZvgU6LcnLnjUO4h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-09_14,2023-06-09_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 mlxscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306090156 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , freedreno@lists.freedesktop.org, Conor Dooley , Krzysztof Kozlowski , devicetree@vger.kernel.org, Sean Paul , Bjorn Andersson , Konrad Dybcio , Abhinav Kumar , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Herring , linux-arm-msm@vger.kernel.org, Dmitry Baryshkov , Marijn Suijten Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, May 29, 2023 at 03:52:28PM +0200, Konrad Dybcio wrote: > > Rename lower_bit to hbb_lo and explain what it signifies. > Add explanations (wherever possible to other tunables). > > Port setting min_access_length, ubwc_mode and hbb_hi from downstream. > > Reviewed-by: Rob Clark > Signed-off-by: Konrad Dybcio > --- > drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 39 +++++++++++++++++++++++++++-------- > 1 file changed, 30 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index dfde5fb65eed..58bf405b85d8 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -786,10 +786,25 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) > static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > { > struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); > - u32 lower_bit = 2; > - u32 amsbc = 0; > + /* Unknown, introduced with A650 family, related to UBWC mode/ver 4 */ > u32 rgb565_predicator = 0; > + /* Unknown, introduced with A650 family */ > u32 uavflagprd_inv = 0; > + /* Whether the minimum access length is 64 bits */ > + u32 min_acc_len = 0; > + /* Entirely magic, per-GPU-gen value */ > + u32 ubwc_mode = 0; > + /* > + * The Highest Bank Bit value represents the bit of the highest DDR bank. > + * We then subtract 13 from it (13 is the minimum value allowed by hw) and > + * write the lowest two bits of the remaining value as hbb_lo and the > + * one above it as hbb_hi to the hardware. This should ideally use DRAM > + * type detection. > + */ > + u32 hbb_hi = 0; > + u32 hbb_lo = 2; > + /* Unknown, introduced with A640/680 */ > + u32 amsbc = 0; > > /* a618 is using the hw default values */ > if (adreno_is_a618(adreno_gpu)) > @@ -800,25 +815,31 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) > > if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) { > /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */ > - lower_bit = 3; > + hbb_lo = 3; > amsbc = 1; > rgb565_predicator = 1; > uavflagprd_inv = 2; > } > > if (adreno_is_7c3(adreno_gpu)) { > - lower_bit = 1; > + hbb_lo = 1; > amsbc = 1; > rgb565_predicator = 1; > uavflagprd_inv = 2; > } > > gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, > - rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1); > - gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1); > - gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, > - uavflagprd_inv << 4 | lower_bit << 1); > - gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21); > + rgb565_predicator << 11 | hbb_hi << 10 | amsbc << 4 | > + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); > + > + gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, hbb_hi << 4 | > + min_acc_len << 3 | hbb_lo << 1 | ubwc_mode); > + > + gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, hbb_hi << 10 | > + uavflagprd_inv << 4 | min_acc_len << 3 | > + hbb_lo << 1 | ubwc_mode); > + > + gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, min_acc_len << 23 | hbb_lo << 21); > } > > static int a6xx_cp_init(struct msm_gpu *gpu) > Reviewed-by: Akhil P Oommen -Akhil > -- > 2.40.1 >