From: Aditya Jain <aditya.jainadityajain.jain@gmail.com>
To: gregkh@linuxfoundation.org
Cc: devel@driverdev.osuosl.org, hdegoede@redhat.com,
Aditya Jain <aditya.jainadityajain.jain@gmail.com>,
linux-kernel@vger.kernel.org, Larry.Finger@lwfinger.net
Subject: [PATCH v2] staging: rtl8723bs: include: Fix coding style issues
Date: Sun, 26 Jul 2020 16:23:02 +0530 [thread overview]
Message-ID: <20200726105302.52188-1-aditya.jainadityajain.jain@gmail.com> (raw)
In-Reply-To: <CAJAoDUjVBon2iiztdER82mHgJtVS6s5XYSajbCTne0KWAzoLvg@mail.gmail.com>
Cleaning messy function declartions and fixing code style
errors in hal_phy_cfg.h as reported by checkpatch.pl
Signed-off-by: Aditya Jain <aditya.jainadityajain.jain@gmail.com>
---
.../staging/rtl8723bs/include/hal_phy_cfg.h | 118 +++++-------------
1 file changed, 33 insertions(+), 85 deletions(-)
diff --git a/drivers/staging/rtl8723bs/include/hal_phy_cfg.h b/drivers/staging/rtl8723bs/include/hal_phy_cfg.h
index 419ddb0733aa..2f123903279c 100644
--- a/drivers/staging/rtl8723bs/include/hal_phy_cfg.h
+++ b/drivers/staging/rtl8723bs/include/hal_phy_cfg.h
@@ -8,54 +8,31 @@
#define __INC_HAL8723BPHYCFG_H__
/*--------------------------Define Parameters-------------------------------*/
-#define LOOP_LIMIT 5
-#define MAX_STALL_TIME 50 /* us */
+#define LOOP_LIMIT 5
+#define MAX_STALL_TIME 50 /* us */
#define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */
#define MAX_TXPWR_IDX_NMODE_92S 63
-#define Reset_Cnt_Limit 3
-
-#define MAX_AGGR_NUM 0x07
+#define Reset_Cnt_Limit 3
+#define MAX_AGGR_NUM 0x07
/*--------------------------Define Parameters End-------------------------------*/
-
/*------------------------------Define structure----------------------------*/
/*------------------------------Define structure End----------------------------*/
/*--------------------------Exported Function prototype---------------------*/
-u32
-PHY_QueryBBReg_8723B(
-struct adapter *Adapter,
-u32 RegAddr,
-u32 BitMask
- );
-
-void
-PHY_SetBBReg_8723B(
-struct adapter *Adapter,
-u32 RegAddr,
-u32 BitMask,
-u32 Data
- );
-
-u32
-PHY_QueryRFReg_8723B(
-struct adapter * Adapter,
-u8 eRFPath,
-u32 RegAddr,
-u32 BitMask
- );
-
-void
-PHY_SetRFReg_8723B(
-struct adapter * Adapter,
-u8 eRFPath,
-u32 RegAddr,
-u32 BitMask,
-u32 Data
- );
+u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask);
+
+void PHY_SetBBReg_8723B(struct adapter *Adapter, u32 RegAddr,
+ u32 BitMask, u32 Data);
+
+u32 PHY_QueryRFReg_8723B(struct adapter *Adapter, u8 eRFPath,
+ u32 RegAddr, u32 BitMask);
+
+void PHY_SetRFReg_8723B(struct adapter *Adapter, u8 eRFPath,
+ u32 RegAddr, u32 BitMask, u32 Data);
/* MAC/BB/RF HAL config */
int PHY_BBConfig8723B(struct adapter *Adapter);
@@ -64,57 +41,28 @@ int PHY_RFConfig8723B(struct adapter *Adapter);
s32 PHY_MACConfig8723B(struct adapter *padapter);
-void
-PHY_SetTxPowerIndex(
-struct adapter * Adapter,
-u32 PowerIndex,
-u8 RFPath,
-u8 Rate
- );
-
-u8
-PHY_GetTxPowerIndex(
-struct adapter * padapter,
-u8 RFPath,
-u8 Rate,
-enum CHANNEL_WIDTH BandWidth,
-u8 Channel
- );
-
-void
-PHY_GetTxPowerLevel8723B(
-struct adapter * Adapter,
- s32* powerlevel
- );
-
-void
-PHY_SetTxPowerLevel8723B(
-struct adapter * Adapter,
-u8 channel
- );
-
-void
-PHY_SetBWMode8723B(
-struct adapter * Adapter,
-enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
-unsigned char Offset /* Upper, Lower, or Don't care */
-);
+void PHY_SetTxPowerIndex(struct adapter *Adapter, u32 PowerIndex,
+ u8 RFPath, u8 Rate);
-void
-PHY_SwChnl8723B(/* Call after initialization */
-struct adapter *Adapter,
-u8 channel
- );
-
-void
-PHY_SetSwChnlBWMode8723B(
-struct adapter * Adapter,
-u8 channel,
-enum CHANNEL_WIDTH Bandwidth,
-u8 Offset40,
-u8 Offset80
+u8 PHY_GetTxPowerIndex(struct adapter *padapter, u8 RFPath, u8 Rate,
+ enum CHANNEL_WIDTH BandWidth, u8 Channel);
+
+void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel);
+
+void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 channel);
+
+void PHY_SetBWMode8723B(struct adapter *Adapter,
+ enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */
+ unsigned char Offset /* Upper, Lower, or Don't care */
);
+/* Call after initialization */
+void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel);
+
+void PHY_SetSwChnlBWMode8723B(struct adapter *Adapter, u8 channel,
+ enum CHANNEL_WIDTH Bandwidth,
+ u8 Offset40, u8 Offset80);
+
/*--------------------------Exported Function prototype End---------------------*/
#endif
--
2.25.1
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next prev parent reply other threads:[~2020-07-26 10:53 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-26 8:02 [PATCH] staging: rtl8723bs: include: Fix coding style errors Aditya Jain
2020-07-26 8:26 ` Greg KH
2020-07-26 8:40 ` Aditya Jain
2020-07-26 10:53 ` Aditya Jain [this message]
2020-07-26 10:59 ` [PATCH v2] staging: rtl8723bs: include: Fix coding style issues Greg KH
2020-07-26 14:18 ` Fix code style issues in staging Aditya Jain
2020-07-26 14:20 ` [PATCH v3 1/4] staging: rtl8723bs: include: Fix coding style errors Aditya Jain
2020-07-26 14:20 ` [PATCH v3 2/4] staging: rtl8723bs: include: Clean up function declations Aditya Jain
2020-07-26 14:20 ` [PATCH v3 3/4] staging: rtl8723bs: include: Further clean up function declarations Aditya Jain
2020-07-26 15:02 ` Greg KH
2020-07-26 17:15 ` Joe Perches
2020-07-26 18:15 ` Aditya Jain
2020-07-28 20:03 ` Aditya Jain
2020-07-26 14:20 ` [PATCH v3 4/4] staging: rtl8723bs: include: Align macro definitions Aditya Jain
2020-07-26 18:03 ` [PATCH] staging: rtl8723bs: include: Fix coding style errors Larry Finger
2020-07-26 18:29 ` Aditya Jain
2020-07-29 19:21 ` [PATCH v4 0/3] Fix coding style issues in staging Aditya Jain
2020-07-29 19:21 ` [PATCH v4 1/3] staging: rtl8723bs: Fix coding style errors Aditya Jain
2020-07-29 19:21 ` [PATCH v4 2/3] staging: rtl8723bs: Clean up function declations Aditya Jain
2020-07-29 19:21 ` [PATCH v4 3/3] staging: rtl8723bs: Align macro definitions Aditya Jain
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