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[83.54.30.67]) by smtp.gmail.com with ESMTPSA id a17sm9663858wrx.63.2021.02.11.23.43.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 11 Feb 2021 23:43:32 -0800 (PST) From: Sergio Paracuellos To: sboyd@kernel.org Subject: [RESEND PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation Date: Fri, 12 Feb 2021 08:43:26 +0100 Message-Id: <20210212074330.4650-3-sergio.paracuellos@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210212074330.4650-1-sergio.paracuellos@gmail.com> References: <20210212074330.4650-1-sergio.paracuellos@gmail.com> MIME-Version: 1.0 X-BeenThere: driverdev-devel@linuxdriverproject.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux Driver Project Developer List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, tsbogend@alpha.franken.de, gregkh@linuxfoundation.org, linux-mips@vger.kernel.org, robh+dt@kernel.org, john@phrozen.org, linux-clk@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: driverdev-devel-bounces@linuxdriverproject.org Sender: "devel" Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml new file mode 100644 index 000000000000..f58d01bdc82c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MT7621 Clock Device Tree Bindings + +maintainers: + - Sergio Paracuellos + +description: | + The MT7621 has a PLL controller from where the cpu clock is provided + as well as derived clocks for the bus and the peripherals. It also + can gate SoC device clocks. + + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + +properties: + compatible: + const: mediatek,mt7621-clk + + "#clock-cells": + description: + The first cell indicates the clock number, see [1] for available + clocks. + const: 1 + + clock-output-names: + maxItems: 8 + +required: + - compatible + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + pll { + compatible = "mediatek,mt7621-clk"; + #clock-cells = <1>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; + }; -- 2.25.1 _______________________________________________ devel mailing list devel@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel