From: Robin Murphy <robin.murphy@arm.com>
To: will@kernel.org, mark.rutland@arm.com
Cc: lorenzo.pieralisi@arm.com, sudeep.holla@arm.com,
linux-arm-kernel@lists.infradead.org, jean-philippe@linaro.org,
leo.yan@linaro.org, noda.akio@socionext.com
Subject: [PATCH 6/6] arm64: dts: Add SMMU PMUs to Juno
Date: Thu, 17 Feb 2022 14:24:20 +0000 [thread overview]
Message-ID: <e33aa6738926a1d2b9cd508c7b16ebbb6994d5b5.1645106346.git.robin.murphy@arm.com> (raw)
In-Reply-To: <cover.1645106346.git.robin.murphy@arm.com>
MMU-401 implements a single counter group, with correspondingly a
single overflow interrupt, which is also muxed into the combined
interrupt output; the integrations in Juno rely on the latter.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
arch/arm64/boot/dts/arm/juno-base.dtsi | 26 ++++++++++++++++++++------
1 file changed, 20 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi
index 6288e104a089..9e242ea84871 100644
--- a/arch/arm64/boot/dts/arm/juno-base.dtsi
+++ b/arch/arm64/boot/dts/arm/juno-base.dtsi
@@ -48,20 +48,25 @@ smmu_pcie: iommu@2b500000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x2b500000 0x0 0x10000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
dma-coherent;
status = "disabled";
+
};
smmu_etr: iommu@2b600000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x2b600000 0x0 0x10000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
dma-coherent;
power-domains = <&scpi_devpd 0>;
};
@@ -638,9 +643,11 @@ smmu_dma: iommu@7fb00000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb00000 0x0 0x10000>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
dma-coherent;
};
@@ -648,27 +655,34 @@ smmu_hdlcd1: iommu@7fb10000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb10000 0x0 0x10000>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
+
};
smmu_hdlcd0: iommu@7fb20000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb20000 0x0 0x10000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
};
smmu_usb: iommu@7fb30000 {
compatible = "arm,mmu-401", "arm,smmu-v1";
reg = <0x0 0x7fb30000 0x0 0x10000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
- #global-interrupts = <1>;
+ #global-interrupts = <2>;
+ #pmu-interrupts = <1>;
dma-coherent;
};
--
2.28.0.dirty
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next prev parent reply other threads:[~2022-02-17 14:36 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-17 14:24 [PATCH 0/6] perf: Arm SMMU PMU driver Robin Murphy
2022-02-17 14:24 ` [PATCH 1/6] iommu/arm-smmu: Account for PMU interrupts Robin Murphy
2022-02-17 14:24 ` [PATCH 2/6] acpi/iort: Register SMMUv2 " Robin Murphy
2022-02-17 14:24 ` [PATCH 3/6] iommu/arm-smmu: Add DT PMU support Robin Murphy
2022-03-02 15:33 ` Rob Herring
2022-03-02 17:03 ` Robin Murphy
2022-02-17 14:24 ` [PATCH 4/6] iommu/smmu: Create child devices for PMUs Robin Murphy
2022-02-17 14:24 ` [PATCH 5/6] perf: Add ARM SMMU PMU driver Robin Murphy
2022-02-17 14:24 ` Robin Murphy [this message]
2022-03-07 22:03 ` [PATCH 0/6] perf: Arm " Will Deacon
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