Re: [PATCH 4/5] x86/sgx: Validate TCS permssions in sgx_validate_secinfo()

From: Jarkko Sakkinen <jarkko.sakkinen@linux.intel.com>
To: Sean Christopherson <sean.j.christopherson@intel.com>
Cc: linux-sgx@vger.kernel.org
Subject: Re: [PATCH 4/5] x86/sgx: Validate TCS permssions in sgx_validate_secinfo()
Date: Fri, 23 Aug 2019 03:57:36 +0300	[thread overview]
Message-ID: <ef15d08e54d62cea3f659e17f0a1b4a881aeb96f.camel@linux.intel.com> (raw)
In-Reply-To: <37fcfdb9f54c01573a83de439e6cbd51ff677649.camel@linux.intel.com>

On Fri, 2019-08-23 at 03:39 +0300, Jarkko Sakkinen wrote:
> On Thu, 2019-08-22 at 09:34 -0700, Sean Christopherson wrote:
> > On Thu, Aug 22, 2019 at 07:31:39PM +0300, Jarkko Sakkinen wrote:
> > > On Wed, 2019-08-21 at 20:55 -0700, Sean Christopherson wrote:
> > > > Why are we validating the TCS protection bits?  Hardware ignores them, so
> > > > why do we care?  sgx_ioc_enclave_add_page() sets the internal protection
> > > > bits so there's no danger of putting the wrong thing in the page tables.
> > > 
> > > I think that in this commit I got it wrong but I think this is awkward:
> > > 
> > > 	/*
> > > 	 * TCS pages must always RW set for CPU access while the SECINFO
> > > 	 * permissions are *always* zero - the CPU ignores the user provided
> > > 	 * values and silently overwrites with zero permissions.
> > > 	 */
> > > 	if ((secinfo.flags & SGX_SECINFO_PAGE_TYPE_MASK) == SGX_SECINFO_TCS)
> > > 		prot |= PROT_READ | PROT_WRITE;
> > > 
> > > In my opinion the right thing to do would be check that SECINFO has *at
> > > minimum* RW and return -EINVAL if not.
> > 
> > Based on Serge's comment, hardware updates MRENCLAVE with SECINFO *after*
> > it overwrites the flags for TCS pages.  I.e. requiring RW for the TCS
> > would result in every enclave failing EINIT due to an invalid measurement.
> > It'd be fairly easy to verify this if we want to triple check that that is
> > indeed hardware behavior.
> 
> This is from the signing tool that I wrote back in 2016 used in the
> selftest:
> 
> struct mreadd {
> 	uint64_t tag;
> 	uint64_t offset;
> 	uint64_t flags; /* SECINFO flags */
> 	uint8_t reserved[40];
> } __attribute__((__packed__));
> 
> static bool mrenclave_eadd(EVP_MD_CTX *ctx, uint64_t offset, uint64_t flags)
> {
> 	struct mreadd mreadd;
> 
> 	memset(&mreadd, 0, sizeof(mreadd));
> 	mreadd.tag = MREADD;
> 	mreadd.offset = offset;
> 	mreadd.flags = flags;
> 
> 	return mrenclave_update(ctx, &mreadd);
> }
> 
> If MRENCLAVE was updated after the overwrite, this would not work.
> 
> The least confusing semantics would be to require RW, no more or less.

OK, it is how Serge said.

This can we verified from the SDM easily (SCRATCH_SECINFO gets zeros
is extended after that).

And also from my signing tool :-)

for (offset = 0; offset < sb.st_size; offset += 0x1000) {
	if (!offset)
		flags = SGX_SECINFO_TCS;
	else
		flags = SGX_SECINFO_REG | SGX_SECINFO_R |
			SGX_SECINFO_W | SGX_SECINFO_X;

OK, so this looks like that my patch does exactly the right thing,
right?

/Jarkko